Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Compiler Estimation of Parallelism and Communication for Quantum Computation

Jeffrey P. Heckey

Published Jan 1, 2014• 0 citations
OpenAlex

Abstract

Quantum computing promises to speed up scientific and computationally intensive operations. However, the power of quantum computing is limited by the relatively small window of time where the quantum state and be maintained (coherent). To achieve maximum efficiency, not merely to keep this state coherent but to increase computational productivity, maximizing the parallelism of the system is important. The architectural model that is explored here attempts to exploit the relatively small number of operations that are actually performed within a quantum computer to maximize fine-grained, data level parallelism, as opposed to the more common coarse-grained, task level parallelism. This model represents a Multi-SIMD processor design, where multiple SIMD cores are used to boost data level parallelism, but allows for limited task indepence.The purpose of this work is to explore the effectiveness of parallel processing in a Multi-SIMD quantum architecture. It examines the ability to speedup computation using a combination of parallel processing scheduling and communication awareness, showing up to 7.8X speedup. This information is then used to extract theoretical requirements for bandwidth (>8000 qubits/cycle peak) and throughput (3 qubits/cycle sustained). This research leverages the ScaffCC compiler toolchain [26], which provides a logical-level (i.e., implicitly error-corrected) quantum assembly output as the input to be scheduled and analyzed.

Related papers

Compiler Management of Communication and Parallelism for Quantum Computation

Jeff Heckey, Shruti R. Patil, Ali Javadi-Abhari +6 more

Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle. Efficient Multi-SIMD operation requires efficient scheduling. This work develops schedulers to reduce communication requirements of qubits between operating regions, while also improving parallelism.We find that communication to global memory is a dominant cost in QC. We also note that many quantum benchmarks have long serial operation paths (although each operation may be data parallel). To exploit this characteristic, we introduce Longest-Path-First Scheduling (LPFS) which pins operations to SIMD regions to keep data in-place and reduce communication to memory. The use of small, local scratchpad memories also further reduces communication. Our results show a 3% to 308% improvement for LPFS over conventional scheduling algorithms, and an additional 3% to 64% improvement using scratchpad memories. Our work is the most comprehensive software-to-quantum toolflow published to date, with efficient and practical scheduling techniques that reduce communication and increase parallelism for full-scale quantum code executing up to a trillion quantum gate operations.

ACM SIGPLAN Notices•Mar 14, 2015•3 citations

Compiler Management of Communication and Parallelism for Quantum Computation

Jeff Heckey, Shruti R. Patil, Ali Javadi-Abhari +6 more

Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle. Efficient Multi-SIMD operation requires efficient scheduling. This work develops schedulers to reduce communication requirements of qubits between operating regions, while also improving parallelism.We find that communication to global memory is a dominant cost in QC. We also note that many quantum benchmarks have long serial operation paths (although each operation may be data parallel). To exploit this characteristic, we introduce Longest-Path-First Scheduling (LPFS) which pins operations to SIMD regions to keep data in-place and reduce communication to memory. The use of small, local scratchpad memories also further reduces communication. Our results show a 3% to 308% improvement for LPFS over conventional scheduling algorithms, and an additional 3% to 64% improvement using scratchpad memories. Our work is the most comprehensive software-to-quantum toolflow published to date, with efficient and practical scheduling techniques that reduce communication and increase parallelism for full-scale quantum code executing up to a trillion quantum gate operations.

ACM SIGARCH Computer Architecture News•Mar 14, 2015•14 citations

Compiler Management of Communication and Parallelism for Quantum Computation

Jeff Heckey, Shruti R. Patil, Ali Javadi-Abhari +6 more

Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle.

International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)•Mar 3, 2015•40 citations

Characterization of quantum workloads on SIMD architectures

Robert Risque, Adwait Jog

There is a growing research interest in quantum computing because of its promise to provide significant performance speedups over classical computers at specialized tasks. While there have been many advances in building more capable, robust, and useful quantum algorithms and software, it is not clear how a scalable, high-performance, and area-efficient quantum architecture should be designed for efficient execution of various quantum workloads. This paper attempts to fill this gap by performing a detailed characterization of many real-world quantum algorithms on SIMDstyle quantum architectures. Specifically, we characterize the effect of size and the number of SIMD regions of a quantum SIMD architecture on various metrics such as performance, utilization, qubit (data) movement etc. We hope that the presented insights on the trade-offs and relationships between aforementioned evaluation metrics will be useful towards designing an efficient and scalable quantum architecture.

IEEE International Symposium on Workload Characterization•Sep 1, 2016•3 citations

Architecting efficiency, performance, and scalability for quantum computers

Margaret Martonosi, Eric C. Chi

This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design. Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC). This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss. Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach. In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.

•Jan 1, 2009•0 citations

Quantum State Superposition-Based Parallel Computing Architecture

Jincheng Zhang

This paper proposes a novel parallel computing architecture leveraging the principles of quantum state superposition. The core concept involves constructing a system where multiple quantum bits are simultaneously placed in superposition states, enabling the parallel execution of computational tasks. This architecture directly addresses the limitations of classical parallel computing by exploiting the inherent parallelism within quantum algorithms. The design focuses on efficiently managing superposition states and facilitating quantum operations for optimal performance. This work presents a foundational framework for future research and development in quantum parallel computing, aiming to significantly enhance computational efficiency for specific problem domains. The architecture's effectiveness hinges on the ability to maintain coherence and accurately manipulate the entangled states generated through superposition. Further investigation into error correction and scalable architectures is crucial for realizing the full potential of this approach.

•Aug 28, 2026•0 citations
Quantum computing promises to speed up scientific and computationally intensive operations. However, the power of quantum computing is limited by the relatively small window of time where the quantum state and be maintained (coherent). To achieve maximum efficiency, not merely to keep this state coherent but to increase computational productivity, maximizing the parallelism of the system is important. The architectural model that is explored here attempts to exploit the relatively small number of operations that are actually performed within a quantum computer to maximize fine-grained, data level parallelism, as opposed to the more common coarse-grained, task level parallelism. This model represents a Multi-SIMD processor design, where multiple SIMD cores are used to boost data level parallelism, but allows for limited task indepence.The purpose of this work is to explore the effectiveness of parallel processing in a Multi-SIMD quantum architecture. It examines the ability to speedup computation using a combination of parallel processing scheduling and communication awareness, showing up to 7.8X speedup. This information is then used to extract theoretical requirements for bandwidth (>8000 qubits/cycle peak) and throughput (3 qubits/cycle sustained). This research leverages the ScaffCC compiler toolchain [26], which provides a logical-level (i.e., implicitly error-corrected) quantum assembly output as the input to be scheduled and analyzed.
Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle. Efficient Multi-SIMD operation requires efficient scheduling. This work develops schedulers to reduce communication requirements of qubits between operating regions, while also improving parallelism.We find that communication to global memory is a dominant cost in QC. We also note that many quantum benchmarks have long serial operation paths (although each operation may be data parallel). To exploit this characteristic, we introduce Longest-Path-First Scheduling (LPFS) which pins operations to SIMD regions to keep data in-place and reduce communication to memory. The use of small, local scratchpad memories also further reduces communication. Our results show a 3% to 308% improvement for LPFS over conventional scheduling algorithms, and an additional 3% to 64% improvement using scratchpad memories. Our work is the most comprehensive software-to-quantum toolflow published to date, with efficient and practical scheduling techniques that reduce communication and increase parallelism for full-scale quantum code executing up to a trillion quantum gate operations.
Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle. Efficient Multi-SIMD operation requires efficient scheduling. This work develops schedulers to reduce communication requirements of qubits between operating regions, while also improving parallelism.We find that communication to global memory is a dominant cost in QC. We also note that many quantum benchmarks have long serial operation paths (although each operation may be data parallel). To exploit this characteristic, we introduce Longest-Path-First Scheduling (LPFS) which pins operations to SIMD regions to keep data in-place and reduce communication to memory. The use of small, local scratchpad memories also further reduces communication. Our results show a 3% to 308% improvement for LPFS over conventional scheduling algorithms, and an additional 3% to 64% improvement using scratchpad memories. Our work is the most comprehensive software-to-quantum toolflow published to date, with efficient and practical scheduling techniques that reduce communication and increase parallelism for full-scale quantum code executing up to a trillion quantum gate operations.
Quantum computing (QC) offers huge promise to accelerate a range of computationally intensive benchmarks. Quantum computing is limited, however, by the challenges of decoherence: i.e., a quantum state can only be maintained for short windows of time before it decoheres. While quantum error correction codes can protect against decoherence, fast execution time is the best defense against decoherence, so efficient architectures and effective scheduling algorithms are necessary. This paper proposes the Multi-SIMD QC architecture and then proposes and evaluates effective schedulers to map benchmark descriptions onto Multi-SIMD architectures. The Multi-SIMD model consists of a small number of SIMD regions, each of which may support operations on up to thousands of qubits per cycle.
There is a growing research interest in quantum computing because of its promise to provide significant performance speedups over classical computers at specialized tasks. While there have been many advances in building more capable, robust, and useful quantum algorithms and software, it is not clear how a scalable, high-performance, and area-efficient quantum architecture should be designed for efficient execution of various quantum workloads. This paper attempts to fill this gap by performing a detailed characterization of many real-world quantum algorithms on SIMDstyle quantum architectures. Specifically, we characterize the effect of size and the number of SIMD regions of a quantum SIMD architecture on various metrics such as performance, utilization, qubit (data) movement etc. We hope that the presented insights on the trade-offs and relationships between aforementioned evaluation metrics will be useful towards designing an efficient and scalable quantum architecture.
This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design. Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC). This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss. Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach. In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
This paper proposes a novel parallel computing architecture leveraging the principles of quantum state superposition. The core concept involves constructing a system where multiple quantum bits are simultaneously placed in superposition states, enabling the parallel execution of computational tasks. This architecture directly addresses the limitations of classical parallel computing by exploiting the inherent parallelism within quantum algorithms. The design focuses on efficiently managing superposition states and facilitating quantum operations for optimal performance. This work presents a foundational framework for future research and development in quantum parallel computing, aiming to significantly enhance computational efficiency for specific problem domains. The architecture's effectiveness hinges on the ability to maintain coherence and accurately manipulate the entangled states generated through superposition. Further investigation into error correction and scalable architectures is crucial for realizing the full potential of this approach.