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IEEE International Conference on Quantum Computing and Engineering (QCE)

Quantifying the Gap Between FPGA and ASIC Implementations of a Surface Code Decoder

Junichiro Kadomoto, Werner Florian, Prasoon Ambalathankandy, Jan-Erik R. Wichmann, Kentaro Sano

Published Aug 30, 2025• 0 citations
Publisher

Abstract

Achieving fault tolerance in quantum computing demands sophisticated control systems, and their development is advancing rapidly. To keep pace with fast-moving qubit technology, these systems are typically prototyped on field-programmable gate arrays (FPGAs)-reconfigurable devices that can adapt to a wide range of qubit counts and connectivity patterns, as well as to various error-correction codes. Nevertheless, application-specific integrated circuits (ASICs)-despite being fixed after fabrication and incurring substantial non-recurring engineering costs-ultimately offer higher performance. This paper presents a case study of the error decoder, a core control system component, and quantitatively compares its FPGA and ASIC implementations. The results offer guidance for future control system design.

DOI
10.1109/qce65121.2025.10488

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•Feb 27, 2025•0 citations
Achieving fault tolerance in quantum computing demands sophisticated control systems, and their development is advancing rapidly. To keep pace with fast-moving qubit technology, these systems are typically prototyped on field-programmable gate arrays (FPGAs)-reconfigurable devices that can adapt to a wide range of qubit counts and connectivity patterns, as well as to various error-correction codes. Nevertheless, application-specific integrated circuits (ASICs)-despite being fixed after fabrication and incurring substantial non-recurring engineering costs-ultimately offer higher performance. This paper presents a case study of the error decoder, a core control system component, and quantitatively compares its FPGA and ASIC implementations. The results offer guidance for future control system design.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
To avoid prohibitive overheads in performing fault-tolerant quantum computation, the decoding problem needs to be solved accurately and at speeds sufficient for fast feedback. Existing decoding systems fail to satisfy both of these requirements, meaning they either slow down the quantum computer or reduce the number of operations that can be performed before the quantum information is corrupted. We introduce the Local Clustering Decoder as a solution that simultaneously achieves the accuracy and speed requirements of a real-time decoding system. Our decoder is implemented on FPGAs and exploits hardware parallelism to keep pace with the fastest qubit types. Further, it comprises an adaptivity engine that allows the decoder to update itself in real-time in response to control signals, such as heralded leakage events. Under a realistic circuit-level noise model where leakage is a dominant error source, our decoder enables one million error-free quantum operations with 4x fewer physical qubits when compared to standard non-adaptive decoding. This is achieved whilst decoding in under 1 μs per round with modest FPGA resources, demonstrating that high-accuracy real-time decoding is possible, and reducing the qubit counts required for large-scale fault-tolerant quantum computation. A key component of quantum error correction is the decoding algorithm, which needs to be accurate but also with a computational overhead that doesn’t lead to backlogs and allows fast logical clock rates. Here, the authors show an FPGA-driven decoder featuring a coarse-grained parallel architecture and on-the-fly error model updates, allowing both high accuracy and real-time operation.
Abstract Belief propagation (BP) combined with ordered statistics decoding (OSD) offers a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly a universal decoder. However, the complexity of OSD can impose timing constraints on real-time decoding for certain quantum technologies, such as superconducting qubits. Recent experiments have demonstrated that larger time budgets are available for the decoding process. Nevertheless, the limits of classical hardware decoder implementations have not been explored. Therefore, the code distance boundaries for different code families that real-time decoders may support remain unknown. For this reason, it is essential to evaluate the architecture of OSD and explore its limits for code families, such as bicycle bivariate codes and surface codes, under realistic assumptions like the detector error model. The findings from this analysis will benefit not only superconducting qubits but also any quantum technology, as improvements will be advantageous when quantum systems scale up. This paper introduces a BP+OSD parallel architecture implemented in both FPGA and ASIC for various surface codes with distances from 3 to 21 and bicycle bivariate codes ranging from distances 6 to 24. Results indicate that decoders for surface codes can fit into a single VCU129 FPGA up to distance 9, achieving a maximum frequency of 200 MHz and a worst-case latency of 134 μs\mu sμs . For bicycle bivariate codes, the limits are found at distance 12, with a maximum frequency of 244 MHz and a worst-case latency of 84 μs\mu sμs. In ASIC technology using a 45nm process, the latency limits improve 31%, and area resources explode for the same code distances, making parallel implementation beyond distance 12 impractical in a single chip.The designs proposed in this work have been verified through a hardware emulator to ensure that the behavior of reference codes matches software simulations within a reasonable logical error rate. The behavior of lower regions, previously unexplored with software, has been examined using emulation down to 10−1210^{-12}10−12 , generating interesting results, such as changes in the decoder slope that suggest the emergence of an error floor when BP+OSD achieves low logical error rates.
To make quantum computers useful and run applications featuring trillions of reliable logical operations, error correction will be required. One of the key components to enable error correction is a decoder that can identify errors which accumulate during the execution of a quantum circuit. The requirements for a decoder are that it accurately detects errors, executes quickly enough as to not create a backlog, and has low power usage so it can scale to millions of qubits and be more easily co-located with the wider qubit control apparatus. In this paper we present a decoder which for a distance 23 rotated planar surface code with 0.1% circuit-level depolarising noise executes in 240ns per round, has a threshold of 0.78%, occupies 0.06mm2 on a CMOS based silicon chip, and consumes less than 8mW of power.
Especially in noisy intermediate-scale quantum (NISQ) devices, fault-tolerant quantum computing cannot be realized without quantum error correction. High error rates in quantum systems stemming from decoherence and gate defects call for effective and flexible QEC systems. This paper presents a novel FPGA-based architecture using dynamic reconfiguration to maximize hardware resources in response to real-time error patterns. Supporting bit-flip, phase-flip, and depolarizing faults among several error correction techniques guarantees high accuracy and little hardware overhead. Scaled for surface code distances up to and beyond, the design combines modular pipelines, adaptive hardware allocation, and error pattern detection. Designed on a Xilinx XC7A50T-CPG236 FPGA, the system showed notable gains over static architecture, averaging 30% lower latency and 20% less resource use overall. Low latency and high throughput are maintained while this dynamic technique enables flexible adaptability to several quantum error models. The outcomes show how well this structure may improve quantum error-correcting systems and enable the incorporation of QEC into useful quantum computer configurations.