IEEE International Conference on Quantum Computing and Engineering (QCE)
A Highly Efficient QEC Decoder Implemented on FPGA and ASIC
Kenton M. Barnes, Tomasz Bialas, Okan Buğdaycı, Earl T. Campbell, Neil I. Gillespie, Kauser Johar, Ram Rajan, Adam W. Richardson, Luka Skorić, Canberk Topal, Mark L. Turner, Abbas B. Ziad
To make quantum computers useful and run applications featuring trillions of reliable logical operations, error correction will be required. One of the key components to enable error correction is a decoder that can identify errors which accumulate during the execution of a quantum circuit. The requirements for a decoder are that it accurately detects errors, executes quickly enough as to not create a backlog, and has low power usage so it can scale to millions of qubits and be more easily co-located with the wider qubit control apparatus. In this paper we present a decoder which for a distance 23 rotated planar surface code with 0.1% circuit-level depolarising noise executes in 240ns per round, has a threshold of 0.78%, occupies 0.06mm2 on a CMOS based silicon chip, and consumes less than 8mW of power.
To make quantum computers useful and run applications featuring trillions of reliable logical operations, error correction will be required. One of the key components to enable error correction is a decoder that can identify errors which accumulate during the execution of a quantum circuit. The requirements for a decoder are that it accurately detects errors, executes quickly enough as to not create a backlog, and has low power usage so it can scale to millions of qubits and be more easily co-located with the wider qubit control apparatus. In this paper we present a decoder which for a distance 23 rotated planar surface code with 0.1% circuit-level depolarising noise executes in 240ns per round, has a threshold of 0.78%, occupies 0.06mm2 on a CMOS based silicon chip, and consumes less than 8mW of power.
Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about 2.78μW when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.
Quantum error correction (QEC) is key to have reliable quantum computation and storage, due to the fragility of qubits in current quantum technology and the imperfect application of quantum operations. In order to have efficient quantum computation and storage, active QEC is required. QEC consists of an encoding and a decoding process. The way that encoding protects quantum information is through grouping many unreliable physical qubits into one more reliable logical qubit. Then, computation occurs based on the logical qubits, however, errors still occur on the physical qubits. Decoding is the process of identifying the location and type of errors occurring on the physical qubits. The decoder proposes corrections against the errors that have been identified. In this thesis, we are exploring novel ways to design decoders for QEC codes, focusing on the surface code. We began our investigation by implementing a rule-based decoder for the smallest surface code, which consists of 17 qubits. We incorporated this decoder to a platform that we created, called Quantum Platform Development Framework (QPDO), in order to study the working principles of a Pauli frame and to quantify its potential effect on the decoding performance. The Pauli frame unit keeps track of errors on physical qubits without the need to apply corrections constantly. We quantified through simulation the benefits in terms of the decoding performance and the execution schedule of QEC, minimizing the idle time. Minimizing the execution time is critical, due to the limited time budget of quantum error correction, thus requiring a high speed decoder capable of still reaching high decoding performance. We show that when the decoding time is equal to the time required to run a surface code cycle, the decoder reaches its maximum performance. However, such a rule-based decoder cannot easily scale to larger quantum systems, therefore other decoding approaches should be considered. Most of the classical decoders that have been developed so far, do not have a good balance between short execution time and high decoding performance. Therefore, we proposed decoders that incorporate neural networks to keep the execution time small, while keeping the decoding performance high. We designed a two-module decoder, which included a classical module and a neural network. We named this configuration neural network based decoder (NNbD). We compare different designs of NNbDs with classical decoders and prove that NNbDs can reach similar or better decoding performance compared to classical decoders while having constant execution time. Furthermore, we quantified the execution time of a NNbD and argued about the speed that can be achieved in a hardware chip like a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC). Both the classical module and the neural network are highly parallelizable and fast modules by construction, leading to constant execution time for a given code distance. We proved that neural network based decoders can adapt to any noise model, since the neural network functionality is based on creating a map between the input and output data, requiring no knowledge about the underlying error model. Following that, a comparison between different NNbD design approaches was performed. We show that it is advantageous to start with a classical decoding module and improve on its decoding performance with a neural network rather than having a neural network perform the decoding on its own. Also, in the latter case, the execution time of such a decoder is non-constant and on average larger than the decoder containing a classical module and a neural network. Moreover, we show that for the design containing a classical module and a neural network, the execution time is increasing linearly as the code distance increased, which was mainly attributed to the increase of the size of the neural network. However, there is a fundamental difference between NNbDs and classical decoders in that NNbDs require sampling and training based on data obtained from the problem, unlike classical decoders. As the code distance increases, the amount of data required to be gathered and trained are exponentially increasing, imposing a limit to the size of the quantum system that can be efficiently decoded. We proposed as a solution to have a distributed decoding approach that divides the code into small regions and then decodes each region locally. We show that using such a distributed decoding approach for small code distances does not lead to significant loss in decoding performance, while simultaneously providing a way to decode large code distances. Thus, we were able to create a decoder that can achieve high decoding performance with constant execution time. However, there are still some issues to keep in mind with such kind of decoders. The main challenge of NNbDs is that they are a dedicated decoder for a given problem. Every time that some aspect of the problem changes (quantum error correcting code, code distance, error model), sampling, training and evaluating the decoder needs to be repeated. Moreover, there is a large number of neural network parameters that need to be specifically tuned when the problem changes. A careful study of the design choices is required to maximize the performance of the decoder. We envision that when sampling and training are performed in hardware, the time required for these processes will be decreased compared to the time required in software. Finally, if the hardware resources allow us to include multiple neural networks, then this can potentially increase the decoding performance. As we presented, dividing the task of decoding to smaller tasks that are distributed to many neural networks can be beneficial.
Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods because it has high fidelity and requires only nearest neighbor qubits connectivity. To realize FTQC, we need a decoder circuit capable of not only QEC in a 3-D lattice to deal with errors in measurement on ancillary qubits but also quantum operations on logically constructed qubits. Whereas several methods to perform logical operations on SC, such as lattice surgery (LS), are known, no practical decoders supporting them have been proposed yet.One of the most promising QC implementations today is made up of superconducting qubits that are located in a cryogenic environment. To reduce the hardware complexity of QC and latency of QEC, we are supposed to perform QEC in a cryogenic environment. Hence a power-efficient decoder is required due to the limited power budget inside a dilution refrigerator.In this paper, we propose an online-QEC algorithm that supports LS with a practical decoder circuit, as well as a new FTQC architecture. We design a key building block of the proposed architecture with a hybrid of SFQ- and Cryo-CMOS-based digital circuits and evaluate it with a SPICE-level simulation. Each logic element includes about 2400 Josephson junctions, and power consumption is estimated to be 2.07 μW when operating with a 2 GHz clock frequency. We evaluate the decoder performance by a quantum error simulator for an essential operation of LS with code distances up to 11, and it achieves a 0.6% accuracy threshold. In an LS-based architecture further supporting a magic-state distillation protocol, which is expected to run for near-term universal quantum computing, we evaluate the QEC performance and power consumption of the architecture and show that it is practical to be operated in 4-K temperature region of a dilution refrigerator.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.