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IMAPSource Proceedings

Simplification of Via-first TSV and Backside Interconnect Process for Large-Scale Superconducting Quantum Annealing Circuits

Naoya Watanabe, Yuuki Araga, Ayuka Morioka, Kunihiko Ishihara, Tomohiro Nishiyama, Katsuya Kikuchi

Published Nov 10, 2025• 0 citations
Publisher

Abstract

We proposed a simplified through-silicon via (TSV) and backside interconnect process to suppress cavity resonance in superconducting quantum annealing circuits. The conventional process consisted of 13 steps, but in the new process, it was reduced to 11 steps by forming TSVs first, then creating the backside interconnect, and finally thinning the wafer to expose the TSVs. The new process comprised the following steps: (a) deep silicon etching using the Bosch process, (b) hole cleaning to remove the photoresist and fluoropolymer residues, (c) CF4 plasma treatment to reduce sidewall scallop, (d) barrier/seed-layer deposition, (e) copper electroplating for TSV filling, (f) backside chemical mechanical polishing (CMP), (g) formation of the superconducting backside interconnect (Ti-Nb-Ti layer), (h) deposition of a backside protection layer, (i) direct Si/Cu grinding, (j) frontside CMP, and (k) fabrication of the quantum annealing circuit. Using this process, we fabricated TSVs (diameter at backside, 60 μm; depth, 395 μm) with superconducting backside interconnects in a 100-mm high-resistivity silicon wafer. Furthermore, we evaluated the effect of TSVs on cavity resonance through high-frequency measurements of samples with and without TSVs. The results demonstrate that the TSVs and backside interconnect of new process effectively suppress cavity resonance.

DOI
10.4071/001c.147098

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We proposed a simplified through-silicon via (TSV) and backside interconnect process to suppress cavity resonance in superconducting quantum annealing circuits. The conventional process consisted of 13 steps, but in the new process, it was reduced to 11 steps by forming TSVs first, then creating the backside interconnect, and finally thinning the wafer to expose the TSVs. The new process comprised the following steps: (a) deep silicon etching using the Bosch process, (b) hole cleaning to remove the photoresist and fluoropolymer residues, (c) CF4 plasma treatment to reduce sidewall scallop, (d) barrier/seed-layer deposition, (e) copper electroplating for TSV filling, (f) backside chemical mechanical polishing (CMP), (g) formation of the superconducting backside interconnect (Ti-Nb-Ti layer), (h) deposition of a backside protection layer, (i) direct Si/Cu grinding, (j) frontside CMP, and (k) fabrication of the quantum annealing circuit. Using this process, we fabricated TSVs (diameter at backside, 60 μm; depth, 395 μm) with superconducting backside interconnects in a 100-mm high-resistivity silicon wafer. Furthermore, we evaluated the effect of TSVs on cavity resonance through high-frequency measurements of samples with and without TSVs. The results demonstrate that the TSVs and backside interconnect of new process effectively suppress cavity resonance.
To realize a large-scale quantum-annealing machine, the size of the quantum annealing circuit chip should be increased. However, when the superconducting circuit chip is large and input signal frequency is high, cavity resonance can occur into the Si chip, causing circuit malfunctions. In this study, we developed a through silicon via (TSV) and backside interconnect process to suppress cavity resonance of the quantum annealing circuit chip. To prevent damage to the superconducting quantum annealing circuit from etching ions and heat during the TSV and backside interconnect formation, we formed the via-first TSVs and backside interconnect before the fabrication of the superconducting quantum annealing circuit. Through this process, TSVs (diameter: 60 µm, depth: 395 µm), including backside interconnects with superconductivity, were formed in a 100 mm high resistivity Si wafer. We also investigated the effect of TSV on the cavity resonance by high-frequency measurement of samples with/without TSVs and backside interconnect. The results demonstrated that the cavity resonance was suppressed by the TSVs and backside interconnect.
Combinatorial optimization problems involve determining the optimal solution from a finite but extremely large number of combinations. Examples include logistics route optimization, drug and material development, and manufacturing process optimization. When solving combinatorial optimization problems using conventional computers with classical bits, calculations are performed for each combination, which requires an extremely long time when the number of combinations is large. Thus, quantum annealing machines are attracting attention as a method for solving this problem because they use quantum bits, which are superpositions of 0 and 1, thereby allowing calculations to be performed in an extremely short time. High-quality quantum bits and quantum-annealing circuits are essential for realizing this quantum-annealing machine. To this end, the NEC Corporation previously developed superconducting quantum annealing circuits using superconducting parametrons to solve combinatorial optimization problems with high speed and accuracy. The use of superconducting parametrons [1,2] renders this quantum-annealing machine resistant to noise and enables a long coherence time, that is, duration for maintaining the quantum state. Furthermore, the NEC Corporation successfully fabricated a superconducting quantum annealing circuit with eight qubit cells using superconducting parametrons and confirmed its operation using aluminum wire bonding technology. However, numerous power supplies and high-frequency signal readouts are required to operate many qubits. In this study, we developed a through-silicon via (TSV) interposer for control and readout of superconducting quantum annealing circuits. This process involves 16 steps: (a) deposition of hard mask; (b) hard mask etching; (c) deep Si etching; (d) hole cleaning to remove the photoresist and hard mask; (e) barrier-seed layer deposition; (e) electroplating for Cu filling; (f) chemical mechanical polishing (CMP), (g) formation of surface protection layer to protect the TSVs; (h) SiO2 bump formation; (i) formation of superconducting frontside interconnect; (j) Ti-In electrode formation; (k) bonding of support glass direct Si/Cu grinding and CMP for backside TSV reveal; (l) formation of backside insulator; (m) formation of backside interconnect with superconductivity (Ti-Al layer); (n) backside passivation layer formation; (o) opening of passivation layer; and (p) Ti-Au electrode formation. Furthermore, we stacked the qubit chips on TSV interposers and evaluated the qubits inside a dilution refrigerator. As a result, we confirmed that controlling the qubits and readout qubit signals via the TSV interposer is possible, and that the qubits operate correctly.
Superconducting through-silicon vias (TSVs), which enable direct signal transmission between circuit layers and reduce spurious coupling, are essential elements in accomplishing a large-scale quantum circuit. However, the widespread adoption of superconducting TSVs has been hindered by fabrication challenges, such as sidewall roughness and complicated process flow. Here, we propose a technique to fabricate superconducting TSVs. With this technique, a single layer of passivated photoresist (PPR) is treated as a hard mask during the Bosch etching process in order to reach an aspect ratio of 20:1 in a 500μm-thick silicon wafer. Compared with other TSV fabrication techniques, using PPR as a hard mask achieves high etching selectivity (80:1), simplifies fabrication process, and yields smooth sidewalls, while remaining compatible with superconducting quantum circuits. To verify superconducting performance, we performed cryogenic measurements on large-diameter TSVs (500μm) that allow uniform aluminum deposition, yielding a critical temperature (TC) of 1.2 K. This technique supports the development of 3D-integrated architectures for superconducting quantum processors, offering a practical pathway toward high-density circuit architectures.
Superconducting through silicon vias are emerging as a key interconnect technology to realise a scalable superconducting quantum computing platform. Integration of semiconductor technology into quantum devices is becoming more common whilst quantum devices are taking advantage of novel combinations of plasma processes and materials to realise more qubits and denser integration. In this letter, plasma processes for fabrication of superconducting niobium nitride TSVs have been developed by means of deep silicon etching, plasma polishing and atomic layer deposition. Key steps were experimentally investigated for their impact on etching and deposition results. The underlying mechanisms have been analysed to optimise the whole process flow. Sidewall topography significantly influenced conformality of niobium nitride deposition into deep features. As a result, high-quality vertical superconducting through silicon vias were obtained with a transition temperature of 10.7 K.
Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.