To realize a large-scale quantum-annealing machine, the size of the quantum annealing circuit chip should be increased. However, when the superconducting circuit chip is large and input signal frequency is high, cavity resonance can occur into the Si chip, causing circuit malfunctions. In this study, we developed a through silicon via (TSV) and backside interconnect process to suppress cavity resonance of the quantum annealing circuit chip. To prevent damage to the superconducting quantum annealing circuit from etching ions and heat during the TSV and backside interconnect formation, we formed the via-first TSVs and backside interconnect before the fabrication of the superconducting quantum annealing circuit. Through this process, TSVs (diameter: 60 µm, depth: 395 µm), including backside interconnects with superconductivity, were formed in a 100 mm high resistivity Si wafer. We also investigated the effect of TSV on the cavity resonance by high-frequency measurement of samples with/without TSVs and backside interconnect. The results demonstrated that the cavity resonance was suppressed by the TSVs and backside interconnect.
To realize a large-scale quantum-annealing machine, the size of the quantum annealing circuit chip should be increased. However, when the superconducting circuit chip is large and input signal frequency is high, cavity resonance can occur into the Si chip, causing circuit malfunctions. In this study, we developed a through silicon via (TSV) and backside interconnect process to suppress cavity resonance of the quantum annealing circuit chip. To prevent damage to the superconducting quantum annealing circuit from etching ions and heat during the TSV and backside interconnect formation, we formed the via-first TSVs and backside interconnect before the fabrication of the superconducting quantum annealing circuit. Through this process, TSVs (diameter: 60 µm, depth: 395 µm), including backside interconnects with superconductivity, were formed in a 100 mm high resistivity Si wafer. We also investigated the effect of TSV on the cavity resonance by high-frequency measurement of samples with/without TSVs and backside interconnect. The results demonstrated that the cavity resonance was suppressed by the TSVs and backside interconnect.
We proposed a simplified through-silicon via (TSV) and backside interconnect process to suppress cavity resonance in superconducting quantum annealing circuits. The conventional process consisted of 13 steps, but in the new process, it was reduced to 11 steps by forming TSVs first, then creating the backside interconnect, and finally thinning the wafer to expose the TSVs. The new process comprised the following steps: (a) deep silicon etching using the Bosch process, (b) hole cleaning to remove the photoresist and fluoropolymer residues, (c) CF4 plasma treatment to reduce sidewall scallop, (d) barrier/seed-layer deposition, (e) copper electroplating for TSV filling, (f) backside chemical mechanical polishing (CMP), (g) formation of the superconducting backside interconnect (Ti-Nb-Ti layer), (h) deposition of a backside protection layer, (i) direct Si/Cu grinding, (j) frontside CMP, and (k) fabrication of the quantum annealing circuit. Using this process, we fabricated TSVs (diameter at backside, 60 μm; depth, 395 μm) with superconducting backside interconnects in a 100-mm high-resistivity silicon wafer. Furthermore, we evaluated the effect of TSVs on cavity resonance through high-frequency measurements of samples with and without TSVs. The results demonstrate that the TSVs and backside interconnect of new process effectively suppress cavity resonance.
Combinatorial optimization problems involve determining the optimal solution from a finite but extremely large number of combinations. Examples include logistics route optimization, drug and material development, and manufacturing process optimization. When solving combinatorial optimization problems using conventional computers with classical bits, calculations are performed for each combination, which requires an extremely long time when the number of combinations is large. Thus, quantum annealing machines are attracting attention as a method for solving this problem because they use quantum bits, which are superpositions of 0 and 1, thereby allowing calculations to be performed in an extremely short time. High-quality quantum bits and quantum-annealing circuits are essential for realizing this quantum-annealing machine. To this end, the NEC Corporation previously developed superconducting quantum annealing circuits using superconducting parametrons to solve combinatorial optimization problems with high speed and accuracy. The use of superconducting parametrons [1,2] renders this quantum-annealing machine resistant to noise and enables a long coherence time, that is, duration for maintaining the quantum state. Furthermore, the NEC Corporation successfully fabricated a superconducting quantum annealing circuit with eight qubit cells using superconducting parametrons and confirmed its operation using aluminum wire bonding technology. However, numerous power supplies and high-frequency signal readouts are required to operate many qubits. In this study, we developed a through-silicon via (TSV) interposer for control and readout of superconducting quantum annealing circuits. This process involves 16 steps: (a) deposition of hard mask; (b) hard mask etching; (c) deep Si etching; (d) hole cleaning to remove the photoresist and hard mask; (e) barrier-seed layer deposition; (e) electroplating for Cu filling; (f) chemical mechanical polishing (CMP), (g) formation of surface protection layer to protect the TSVs; (h) SiO2 bump formation; (i) formation of superconducting frontside interconnect; (j) Ti-In electrode formation; (k) bonding of support glass direct Si/Cu grinding and CMP for backside TSV reveal; (l) formation of backside insulator; (m) formation of backside interconnect with superconductivity (Ti-Al layer); (n) backside passivation layer formation; (o) opening of passivation layer; and (p) Ti-Au electrode formation. Furthermore, we stacked the qubit chips on TSV interposers and evaluated the qubits inside a dilution refrigerator. As a result, we confirmed that controlling the qubits and readout qubit signals via the TSV interposer is possible, and that the qubits operate correctly.
Superconducting through-silicon vias (TSVs), which enable direct signal transmission between circuit layers and reduce spurious coupling, are essential elements in accomplishing a large-scale quantum circuit. However, the widespread adoption of superconducting TSVs has been hindered by fabrication challenges, such as sidewall roughness and complicated process flow. Here, we propose a technique to fabricate superconducting TSVs. With this technique, a single layer of passivated photoresist (PPR) is treated as a hard mask during the Bosch etching process in order to reach an aspect ratio of 20:1 in a 500μm-thick silicon wafer. Compared with other TSV fabrication techniques, using PPR as a hard mask achieves high etching selectivity (80:1), simplifies fabrication process, and yields smooth sidewalls, while remaining compatible with superconducting quantum circuits. To verify superconducting performance, we performed cryogenic measurements on large-diameter TSVs (500μm) that allow uniform aluminum deposition, yielding a critical temperature (TC) of 1.2 K. This technique supports the development of 3D-integrated architectures for superconducting quantum processors, offering a practical pathway toward high-density circuit architectures.
Quantum annealing (QA) is a computing paradigm for solving combinatorial optimization problems by finding the low-energy configurations of complicated Ising models through quantum fluctuation. Recently, because of the strictly limited number of superconducting qubits per chip, three-dimensional (3D) integrated technologies have attracted great attention for realizing a practical large-scale QA machine. Because a cryogenic environment is required for qubit chip operation, the less-effective heat transfer in the stacked structure has become a major concern. In the present paper, a method to realize a sufficiently low temperature for quantum operation in large-scale superconducting QA machines based on 3D packaging technology is proposed and demonstrated numerically. We reveal that the heating in such a 3D structure, which seriously reduces the quantum coherence of qubit chips, is effectively prevented by adding through-silicon vias (TSVs). Accordingly, the temperature of the qubit chip is drastically reduced from 57.8 mK to 16.4 mK. Our results indicate that using TSVs are a powerful and simple approach to realizing practical large-scale superconducting QA machines.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.