Demonstration of Two-Dimensional Connectivity for a Scalable Error-Corrected Ion-Trap Quantum Processor Architecture
Marco Valentini, Martin W. van Mourik, Friederike Butt, J. Wahl, Matthias Dietl, M. Pfeifer, Fabian Anmasser, Yves Colombe, Clemens Rössler, Philip C. Holz, R. Blatt, A. Bermúdez, Markus Müller, Thomas Monz, Philipp Schindler
A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the quantum spring array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.
A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the quantum spring array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.
A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the Quantum Spring Array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.
Microfabricated ion trap chips are at the core of some of the most advanced quantum computers. How a large number of ions is arranged and controlled on an ion trap chip depends on the chosen trap architecture. One such architecture is the quantum spring array (QSA). In the QSA architecture, ion chains are arranged in a two-dimensional lattice and interact with ion chains in neighboring sites in the radial and axial directions of the respective chain. This interaction, or coupling, is mediated by the Coulomb force while keeping ions in separate trapping sites, and scales inversely with the third power of the separation. The capability to control the distance between ions in the lattice is thus essential. In previous works, the radial separation between ions was tuned by controlling the rf pseudo-potential, which revealed to be experimentally challenging to realize while maintaining low heating rates. In this work, we present an ion trap chip design that allows tuning of the radial distance between ions using only dc voltages. The radial transport is executed between different interaction zones, designated for quantum operations, through specifically designed transition zones. A prototype of this type of ion trap chip was microfabricated on fused silica substrate. Its functionality is characterized by demonstrating dc-controlled radial transport of a single ion through a transition zone and measuring stray fields and ion heating rates in the center of the trap. Moreover, the fabrication of a multi-metal layer version of such a trap is presented as a scaling path for the presented chip design.
Qubits based on ions trapped in linear radio-frequency traps form a successful platform for quantum computing, due to their high fidelity of operations, all-to-all connectivity, and degree of local control. In principle, there is no fundamental limit to the number of ion-based qubits that can be confined in a single 1D register. However, in practice, there are two main issues associated with long trapped-ion crystals, that stem from the “softening” of their modes of motion, upon scaling up: high heating rates of the ions’ motion and a dense motional spectrum; both impede the performance of high-fidelity qubit operations. Here, we propose a holistic, scalable architecture for quantum computing with large ion crystals that overcomes these issues. Our method relies on dynamically operated optical potentials that instantaneously segment the ion crystal into cells of a manageable size. We show that these cells behave as nearly independent quantum registers, allowing for parallel entangling gates on all cells. The ability to reconfigure the optical potentials guarantees connectivity across the full ion crystal and also enables efficient midcircuit measurements. We study the implementation of large-scale parallel multiqubit entangling gates that operate simultaneously on all cells and present a protocol to compensate for crosstalk errors, enabling full-scale usage of an extensively large register. We illustrate that this architecture is advantageous both for fault-tolerant digital quantum computation and for analog quantum simulations. Published by the American Physical Society 2024
Realising large-scale quantum computation in the near future will require increasing the number of low-error two-qubit gates that can be implemented on a quantum computer before decoherence. One of the biggest challenges facing current trapped ion quantum computers is implementing high-speed two-qubit operations, whilst increasing the number of qubits. One of the most promising proposals for overcoming current limitations is the use of ultra-fast pulses to implement fast two-qubit gates between nearest-neighbour pairs of ions. In this thesis, I investigate these ‘fast gates’ in two-dimensional arrays of microtraps, each containing a single ion. I argue that two-dimensional architectures allow for a significant reduction in the number of two-qubit gates required for a particular computation, as compared to one-dimensional ion chains. I demonstrate this reduction for a quantum simulation of a 40-mode Fermi-Hubbard Hamiltonian. I develop an efficient scheme that allows fast gates to be numerically optimised for two-dimensional geometries. I find that this optimisation scheme is capable of designing gates that are faster, higher fidelity, and require lower laser repetition rates. Using this scheme, I find that high-speed two-qubit gates can be optimised for two-dimensional architectures, with fidelities well above thresholds required for fault tolerant error correction, around 99.99%. Furthermore, I find that fast gates in these architectures are robust to the presence of large numbers of surrounding ions. Following previous studies [1, 2] which have identified pulse imperfections as a dominant source of error in fast gates, I perform a worst-case error analysis. I find the fast gates presented in this thesis to require very small errors in single-qubit rotations, and I present recommendations for achieving those requirements. I also investigate other experimental considerations, and make recommendations for overcoming other technical challenges in realising fast gates.
We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as 10−8 with the [[31,1,7]] color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.