We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as $10^{-8}$ with the $[[31, 1, 7]]$ color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.
We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as 10−8 with the [[31,1,7]] color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.
Quantum error correction enables scalable fault-tolerant quantum computation by suppressing logical errors exponentially with code distance once physical error rates fall below a critical threshold. Here we demonstrate below-threshold operation of triangular color codes with distances d=3,5, and 7 on Quantinuum's Helios trapped-ion quantum processor. Leveraging both circuit- and hardware- level leakage reduction schemes, we achieve logical error rates as low as 5−2+4×10−6, and demonstrate error suppression by over an order of magnitude, Λ=12−2+3, with each successive increase in code distance. Moreover, we demonstrate below threshold scaling of error rates for Clifford two-qubit randomized benchmarking circuits when encoded in d=3,5 color codes, achieving logical error rate of 7−3+3×10−5 per logical two-qubit Clifford at distance 5 with a suppression factor of Λ=9−3+8. We compare logical performance for existing near-optimal algorithmic decoders, and both convolutional neural network and transformer-based neural network decoders capable of real-time decoding an order of magnitude faster than the syndrome extraction rate. These results approach the logical error rates required for megaquop-scale quantum computation and indicate that scaled trapped-ion processors could reach application-relevant performance with substantially smaller code blocks than indicated by previous results in other qubit modalities.
Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the [[20,2,6]]C4-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of 4.6−2.6+6.2×10−5 per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of 2.8−1.6+1.0×10−4 per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between C4-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925−0.245+0.068%. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the 10−6-10−8 logical-error regime targeted for early fault-tolerant computation. Together, these results establish C4-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.
Exploiting recent advances in quantum trapped-ion technologies, we propose a scalable, fault-tolerant quantum computing architecture that overcomes the fundamental challenges of building a full-scale quantum computer and leaves the fabrication a daunting but primarily an engineering concern. Using a hierarchical array-based design and a quantum teleportation communication protocol, we are able to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution. In particular, we present a reconfigurable quantum circuit substrate, or "quantum FPGA'' (qFPGA) which allows efficient implementation of universal quantum gates and error correction. We use this qFPGA as a basic building block for an array structure that scalably provides communication channels and quantum resource distribution. We exploit a hierarchical combination of ballistic transport of data ions and quantum teleportation to reduce the cost of reliable communication from exponential to polynomial in distance. By using a set of simulation tools we are able to evaluate a hypothetical design of a future general purpose quantum computer and describe the execution of a fault-tolerant Toffoli gate construction. Without considering classical control constraints and assuming best-possible ion-trap parameters our computer consists of level 2 encoded qubits with the Steane \ecc code tightly connected by the teleportation interconnect, and capable of executing a fault-tolerant Toffoli gate in roughly 2.3 seconds. This translates to factoring a 128-bit number in slightly over 40 hours in circuits dominated by Toffoli gates.
Quantum error correction requires the detection of errors via reliable measurements of multiqubit correlation operators.As these operations are inherently faulty, fault-tolerant schemes for realizing quantum error correction are required.Recently, a paradigm requiring only minimal resource overhead in the form of "flag" qubits to detect and correct errors has been proposed.We experimentally demonstrate a fault-tolerant weight-4 parity-check measurement scheme, where one additional flag qubit serves to detect errors, which would otherwise proliferate into uncorrectable weight-2 errors onto the qubit register.We achieve a parity measurement fidelity of 92.3(2)%, which increases to 93.2(2)% upon conditioning to the flag readout result, which shows that the measurement scheme intercepts intrinsic errors occurring throughout the sequence.We show that the protocol is capable of reliably intercepting faults by deliberately injecting bit-and phase-flip errors.For holistic benchmarking of the parity measurement scheme, we use an entanglement witnessing scheme requiring a minimal number of measurements to verify genuine six-qubit multipartite entanglement.The demonstrated fault-tolerant parity measurement scheme constitutes the key building block in a broad class of resource-efficient flag-based quantum error correction protocols including topological color codes.Our hardware platform is based on atomic ions stored in a microchip ion trap.The qubit register is dynamically reconfigured via shuttling operations enabling effective full connectivity without operational cross talk, thereby providing key prerequisites underlying fault-tolerant circuit design.These architectural features in combination with the demonstrated approach to flag-based fault-tolerant quantum error correction open up a route toward scalable fault-tolerant quantum computing.
A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the quantum spring array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.
Fault-tolerant quantum computing requires not only reliable logical qubit storage, but also the ability to perform high-fidelity logical operations between error-corrected qubits at scale. While much of the existing literature focuses on optimizing syndrome extraction for a single logical qubit, the co-design of physical architectures that support both robust error correction and efficient logical computation remains an open challenge. In this work, we propose a multi-qubit spin-qubit shuttling bus architecture that addresses both requirements simultaneously. The architecture optimizes the physical qubit layout for syndrome extraction and supports transversal two-qubit logical gates between an arbitrary number of logical qubits, achieving all-to-all logical connectivity through coherent spin shuttling. We further propose an ancilla-sharing scheme that encodes multiple logical qubits within a single logical element, compressing the physical footprint of the processor and improving long-range gate fidelity. Extending the architecture from a one-dimensional bus to a two-dimensional grid of shuttling tracks reduces the inter-qubit distance, yielding consistent improvements in logical error. Finally, we apply the Quantum Reverse Mapping methodology at the logical level to optimize the layout of a \textit{15-to-1} magic state distillation circuit, demonstrating how the transversal capabilities of the proposed architecture can be leveraged for universal fault-tolerant computation. Taken together, these results establish a principled co-design framework that bridges the physical, error-correction, and logical computation layers of the quantum stack, and demonstrate that spin-qubit shuttling architectures are a viable and flexible substrate for scalable fault-tolerant quantum computation.