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Physical Review X

Fault-Tolerant Parity Readout on a Shuttling-Based Trapped-Ion Quantum Computer

Janine Hilder, D. R. M. Pijn, O. Onishchenko, Alexander Stahl, M. Orth, Bjoern Lekitsch, A. Blanco, Markus Müller, Ferdinand Schmidt‐Kaler, Ulrich Poschinger

Published Feb 17, 2022• 66 citations
Publisher

Abstract

Quantum error correction requires the detection of errors via reliable measurements of multiqubit correlation operators.As these operations are inherently faulty, fault-tolerant schemes for realizing quantum error correction are required.Recently, a paradigm requiring only minimal resource overhead in the form of "flag" qubits to detect and correct errors has been proposed.We experimentally demonstrate a fault-tolerant weight-4 parity-check measurement scheme, where one additional flag qubit serves to detect errors, which would otherwise proliferate into uncorrectable weight-2 errors onto the qubit register.We achieve a parity measurement fidelity of 92.3(2)%, which increases to 93.2(2)% upon conditioning to the flag readout result, which shows that the measurement scheme intercepts intrinsic errors occurring throughout the sequence.We show that the protocol is capable of reliably intercepting faults by deliberately injecting bit-and phase-flip errors.For holistic benchmarking of the parity measurement scheme, we use an entanglement witnessing scheme requiring a minimal number of measurements to verify genuine six-qubit multipartite entanglement.The demonstrated fault-tolerant parity measurement scheme constitutes the key building block in a broad class of resource-efficient flag-based quantum error correction protocols including topological color codes.Our hardware platform is based on atomic ions stored in a microchip ion trap.The qubit register is dynamically reconfigured via shuttling operations enabling effective full connectivity without operational cross talk, thereby providing key prerequisites underlying fault-tolerant circuit design.These architectural features in combination with the demonstrated approach to flag-based fault-tolerant quantum error correction open up a route toward scalable fault-tolerant quantum computing.

DOI
10.1103/physrevx.12.011032

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Quantum error correction requires the detection of errors via reliable measurements of multiqubit correlation operators.As these operations are inherently faulty, fault-tolerant schemes for realizing quantum error correction are required.Recently, a paradigm requiring only minimal resource overhead in the form of "flag" qubits to detect and correct errors has been proposed.We experimentally demonstrate a fault-tolerant weight-4 parity-check measurement scheme, where one additional flag qubit serves to detect errors, which would otherwise proliferate into uncorrectable weight-2 errors onto the qubit register.We achieve a parity measurement fidelity of 92.3(2)%, which increases to 93.2(2)% upon conditioning to the flag readout result, which shows that the measurement scheme intercepts intrinsic errors occurring throughout the sequence.We show that the protocol is capable of reliably intercepting faults by deliberately injecting bit-and phase-flip errors.For holistic benchmarking of the parity measurement scheme, we use an entanglement witnessing scheme requiring a minimal number of measurements to verify genuine six-qubit multipartite entanglement.The demonstrated fault-tolerant parity measurement scheme constitutes the key building block in a broad class of resource-efficient flag-based quantum error correction protocols including topological color codes.Our hardware platform is based on atomic ions stored in a microchip ion trap.The qubit register is dynamically reconfigured via shuttling operations enabling effective full connectivity without operational cross talk, thereby providing key prerequisites underlying fault-tolerant circuit design.These architectural features in combination with the demonstrated approach to flag-based fault-tolerant quantum error correction open up a route toward scalable fault-tolerant quantum computing.
Quantum error correction requires the detection of errors by reliable measurements of suitable multi-qubit correlation operators. Here, we experimentally demonstrate a fault-tolerant weight-4 parity check measurement scheme. An additional 'flag' qubit serves to detect errors occurring throughout the parity measurement, which would otherwise proliferate into uncorrectable weight-2 errors on the qubit register. We achieve a flag-conditioned parity measurement single-shot fidelity of 93.2(2)\%. Deliberately injecting bit and phase-flip errors, we show that the fault-tolerant protocol is capable of reliably intercepting such faults. For holistic benchmarking of the parity measurement scheme, we use entanglement witnessing to show that the implemented circuit generates genuine six-qubit multi-partite entanglement. The fault-tolerant parity measurement scheme is an essential building block in a broad class of stabilizer quantum error correction protocols, including topological color codes. Our hardware platform is based on atomic ions stored in a segmented microchip ion trap. The qubit register is dynamically reconfigured via shuttling operations, enabling effective full connectivity without operational cross-talk, which provides key capabilities for scalable fault-tolerant quantum computing.
Logical qubits can be protected from decoherence by performing QEC cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory that operates for in principle arbitrary long times. All circuit components must be assumed as noisy unless specific assumptions about the form of the noise are made. Modern QEC schemes are challenging to implement experimentally in physical architectures where in-sequence measurements and feed-forward of classical information cannot be reliably executed fast enough or even at all. Here we provide a novel scheme to perform QEC cycles without the need of measuring qubits that is fully fault-tolerant with respect to all components used in the circuit. Our scheme can be used for any low-distance CSS code since its only requirement towards the underlying code is a transversal CNOT gate. Similarly to Steane-type EC, we coherently copy errors to a logical auxiliary qubit but then apply a coherent feedback operation from the auxiliary system to the logical data qubit. The logical auxiliary qubit is prepared fault-tolerantly without measurements, too. We benchmark logical failure rates of the scheme in comparison to a flag-qubit based EC cycle. We map out a parameter region where our scheme is feasible and estimate physical error rates necessary to achieve the break-even point of beneficial QEC with our scheme. We outline how our scheme could be implemented in ion traps and with neutral atoms in a tweezer array. For recently demonstrated capabilities of atom shuttling and native multi-atom Rydberg gates, we achieve moderate circuit depths and beneficial performance of our scheme while not breaking fault tolerance. These results thereby enable practical fault-tolerant QEC in hardware architectures that do not support mid-circuit measurements.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
The construction of a quantum computer remains a fundamental scientific and technological challenge because of the influence of unavoidable noise. Quantum states and operations can be protected from errors through the use of protocols for quantum computing with faulty components. We present a quantum error-correcting code in which one qubit is encoded in entangled states distributed over seven trapped-ion qubits. The code can detect one bit flip error, one phase flip error, or a combined error of both, regardless on which of the qubits they occur. We applied sequences of gate operations on the encoded qubit to explore its computational capabilities. This seven-qubit code represents a fully functional instance of a topologically encoded qubit, or color code, and opens a route toward fault-tolerant quantum computing.
Building fault-tolerant quantum computers with large numbers of logical qubits requires both scalable hardware architectures and error-correcting codes that make efficient use of physical qubits. Photonic interconnects address both of these challenges by allowing the physical qubits to be distributed across multiple processors while providing the non-local connectivity necessary to implement resource-efficient codes such as high-rate quantum low-density parity-check (qLDPC) codes. A key requirement for realising this architecture is the ability to perform stabiliser measurements between remote processors, which has not previously been demonstrated experimentally. Here we report the first experimental demonstration of distributed quantum error detection and correction. We generate entanglement between network qubits in two separate trapped-ion processors and use it to perform remote syndrome measurements on data qubits. We first realise a distributed [[2, 1, 1]] repetition code, detecting phase-flip errors on a logical qubit encoded across the two modules in real time and suppressing logical errors. We then combine these mid-circuit syndrome measurements with real-time feedforward to actively correct arbitrary single-qubit Pauli errors on a distributed Bell state. These results provide an experimental foundation for quantum error correction (QEC) across modular quantum architectures.
We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as 10−810^{-8}10−8 with the [[31,1,7]][[31, 1, 7]][[31,1,7]] color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.