Demonstration of the QCCD trapped-ion quantum computer architecture
Juan Miguel Rey Pino, Joan Dreiling, Caroline Figgatt, John Gaebler, Steven A. Moses, Michael S. Allman, Charles H. Baldwin, Michael Foss‐Feig, David Hayes, Karl Mayer, Ciarán Ryan-Anderson, Brian Neyenhuis
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of $2^6=64$. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.
Quantinuum has deployed trapped-ion quantum computers based on a quantum charge-coupled (QCCD) architecture exhibiting high-fidelity operations, mid-circuit measurements, and full connectivity with record performance. Quantinuum recently released its accelerated Roadmap outlining plans to reach thousands of physical qubits while further reducing logical qubit error rates in commercial systems by 2029 [1]. Longerterm scaling of the QCCD device architecture will be enabled by replacing bulk free-space optics with integrated photonics for improved light delivery and detection. To this end, Quantinuum is developing integrated photonics technologies at the visible and ultraviolet wavelengths required for future large-scale trapped-ion quantum computers. This poster presents recent developments in materials (waveguiding materials, transparent conductive materials), visible and ultraviolet integrated photonics components for light routing and control, and the various paths to their implementation. These developments are expected to enable scaling towards larger qubit counts while reducing the physical size of the optical control systems.
Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.
Trapped ions (TIs) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies, featuring high qubit quality, coherence time, and qubit connectivity. However, current TI systems are small in size and typically use a single trap architecture, which has fundamental scalability limitations. To progress toward the next major milestone of 50--100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50--100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology, and gate implementations and the need to match diverse application resource requirements. Toward realizing QCCD-based TI systems with 50--100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology, and operation implementation methods. To enable our study, we built a design toolflow, which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability, and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near future and accelerate the progress toward practical QC systems.
Qubits based on ions trapped in linear radio-frequency traps form a successful platform for quantum computing, due to their high fidelity of operations, all-to-all connectivity, and degree of local control. In principle, there is no fundamental limit to the number of ion-based qubits that can be confined in a single 1D register. However, in practice, there are two main issues associated with long trapped-ion crystals, that stem from the “softening” of their modes of motion, upon scaling up: high heating rates of the ions’ motion and a dense motional spectrum; both impede the performance of high-fidelity qubit operations. Here, we propose a holistic, scalable architecture for quantum computing with large ion crystals that overcomes these issues. Our method relies on dynamically operated optical potentials that instantaneously segment the ion crystal into cells of a manageable size. We show that these cells behave as nearly independent quantum registers, allowing for parallel entangling gates on all cells. The ability to reconfigure the optical potentials guarantees connectivity across the full ion crystal and also enables efficient midcircuit measurements. We study the implementation of large-scale parallel multiqubit entangling gates that operate simultaneously on all cells and present a protocol to compensate for crosstalk errors, enabling full-scale usage of an extensively large register. We illustrate that this architecture is advantageous both for fault-tolerant digital quantum computation and for analog quantum simulations. Published by the American Physical Society 2024