Demonstration of the trapped-ion quantum CCD computer architecture
J. M. Pino, Joan Dreiling, Caroline Figgatt, John Gaebler, Steven A. Moses, Michael S. Allman, Charles H. Baldwin, Michael Foss‐Feig, David Hayes, Karl Mayer, Ciarán Ryan-Anderson, Brian Neyenhuis
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Trapped-ion quantum computers exhibit promising potential to provide platforms for high-quality qubits and reliable quantum computation. The quantum charge coupled device (QCCD) architecture is a leading example that offers a modular solution to enable the realization of scalable quantum computers, paving the way for practical quantum algorithms with large qubit numbers. Within these devices, ions can be shuttled (moved) throughout the trap and through different dedicated zones, e.g., a memory zone for storage and a processing zone for the actual computation. However, due to decoherence of the ions’ quantum states, the qubits lose their quantum information over time. Thus, the required time steps of shuttling operations should be minimized. In this work,1 we propose a heuristic approach to determining an efficient shuttling schedule, which orchestrates the movement operations within the device. Given a quantum algorithm and a device architecture, the proposed approach produces shuttling schedules with a close-to-minimal amount of time steps for small-size QCCD architectures. For large-scale QCCD devices, empirical evaluations show promising results with respect to quality of the solution as well as performance. An implementation of the proposed approach is publicly available as part of the open-source Munich Quantum Toolkit (MQT) athttps://github.com/cda-tum/mqt-ion-shuttler.
The Quantum Charge Coupled Device (QCCD) architecture is a promising pathway toward scalable quantum computation in trapped-ion quantum computers. Devices using this architecture rely on efficient ion shuttling between memory and processing zones to execute quantum circuits. Hardware for trapped-ion quantum computers with multiple different zones is already being developed, but without proper compilation support, there is a risk that we will not be able to use their full potential. Recent approaches to shuttling algorithms have primarily focused on small architectures or devices with a single processing zone. In this work, we propose to extend these algorithms to large grid-type systems with multiple processing zones embedded in the memory zone. For that, a two-step solution is described: first, partitioning quantum circuits to determine where each gate is executed, and second, adapting a publicly available shuttling algorithm for architectures with a single processing zone to handle the increased complexity of multi-zone systems. Empirical evaluations demonstrate the method's effectiveness across a range of grid-type architectures, showing that additional processing zones can significantly reduce quantum circuit execution time. With that, we provide a foundation for the compilation of shuttling-based trapped-ion quantum computers with multiple processing zones. An open-source implementation of the proposed approach is available at https://github.com/cda-tum/mqt-ion-shuttler.
Trapped-ion quantum computers are a promising platform, offering high-quality qubits with long coherence times and high-fidelity gate operations. The Quantum Charge Coupled Device (QCCD) architecture provides a scalable blueprint by leveraging the ability to shuttle ions between distinct zones. However, realizing such architectures in practice requires software support to manage ion movement across multi-zone layouts. In this work, we propose a compilation strategy for QCCD architectures with multiple processing zones located outside a grid-type memory zone. Unlike previous approaches that treat processing zones as black-boxes, our method explicitly models their structural constraints, enabling optimized ion movement to and through them. It combines qubit partitioning with dependency-aware gate selection to reduce inter-zone shuttling while enabling simultaneous gate execution. We implemented the method in an open-source tool and empirically demonstrated its effectiveness across several QCCD layouts, laying a foundation for the compilation of multi-zone trapped-ion systems.
Trapped-ion quantum computers hold significant promise as platforms for high-quality qubits and reliable quantum computation. The Quantum Charge Coupled Device (QCCD) architecture shows potential in enabling scalable trapped-ion quantum computers through its modular design. Within QCCD devices, ions can be shuttled throughout the trap, which is divided into different dedicated zones, e.g. a memory zone for storage and a processing zone for actual computation. While the modular approach shows promise, designing a large-scale QCCD device remains challenging due to the numerous possibilities involved in designing the precise architecture of the hardware. In this work, we propose leveraging existing compilers to evaluate design choices in the development of QCCD architectures. Rather than compiling specifically for a single device, we use the compiler to explore and evaluate the execution of representative quantum circuits on various architectures. This allows for a fast assessment of different design choices, considering individual requirements and physical limitations. To validate the feasibility of this idea, we conducted a study focusing on key design decisions, including system size, junction density, processing zone positioning, and the benefits of SWAP operations within the memory zone. Based on these results, we are able to provide first recommendations and insights for the design of future QCCD architectures.
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.