Calibration of a quantum computer is the process of optimizing its control parameters to ensure the accurate implementation of quantum gates.It remains a critical challenge in scaling quantum computers.Existing calibration methods take a generalized approach that focuses on the trade-off between calibration time and fidelity.However, these methods lack the awareness of hardware differences among physical qubits and an elaborate design of parallel calibration.In this paper, we introduce a fine-grained calibration protocol that contains three calibration policies for hardware differences and a method to enable parallel calibration.We begin by profiling qubit pairs to evaluate their responses to different waveform candidates.Based on profiling results, we determine the best calibration policy for the quantum computer, which is the first part of the calibration protocol.The second part of our protocol is to use graph traverse to enable parallel calibration by identifying compatible calibration operations.We validate our protocol through intensive experiments on real quantum machines with up to 127 qubits.Our experimental results demonstrate a 1.84× reduction in terms of the medium of the two-qubit gate error rate, 1.26× reduction in pulse duration, an 8× to 25× reduction in total calibration overhead compared with sequential calibration, an average of 2.12× further reduction in total calibration overhead owing to profiling policy, double of the quantum volume, and a 2.0× to 2.3× reduction in error per layered gate.The proposed protocol emphasizes the importance of hardware-aware and parallel calibration and advances current quantum computers towards fault-tolerant quantum computing.
Calibration of a quantum computer is the process of optimizing its control parameters to ensure the accurate implementation of quantum gates.It remains a critical challenge in scaling quantum computers.Existing calibration methods take a generalized approach that focuses on the trade-off between calibration time and fidelity.However, these methods lack the awareness of hardware differences among physical qubits and an elaborate design of parallel calibration.In this paper, we introduce a fine-grained calibration protocol that contains three calibration policies for hardware differences and a method to enable parallel calibration.We begin by profiling qubit pairs to evaluate their responses to different waveform candidates.Based on profiling results, we determine the best calibration policy for the quantum computer, which is the first part of the calibration protocol.The second part of our protocol is to use graph traverse to enable parallel calibration by identifying compatible calibration operations.We validate our protocol through intensive experiments on real quantum machines with up to 127 qubits.Our experimental results demonstrate a 1.84× reduction in terms of the medium of the two-qubit gate error rate, 1.26× reduction in pulse duration, an 8× to 25× reduction in total calibration overhead compared with sequential calibration, an average of 2.12× further reduction in total calibration overhead owing to profiling policy, double of the quantum volume, and a 2.0× to 2.3× reduction in error per layered gate.The proposed protocol emphasizes the importance of hardware-aware and parallel calibration and advances current quantum computers towards fault-tolerant quantum computing.
In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.
The ability to coherently and reliably manipulate quantum information marks a fundamental technological leap—realizable through a universal, fault‑tolerant quantum computer. Achieving this goal requires progress across all layers of the quantum computing stack, from physical qubits to theoretical algorithms. In this work, we address multiple layers of this stack. We develop a software architecture for scalable device calibration using modular calibration graphs. We introduce real‑time frequency stabilization techniques, demonstrating improved single‑qubit gate fidelities and progress toward multiqubit feedback. Finally, we explore how quantum error correction overhead can be reduced using low‑density parity‑check codes. We present logical protocols for a non‑local nine‑qubit code, which significantly outperforms comparable surface code implementations in both qubit efficiency and computational capability. These results represent practical steps toward overcoming key challenges in fault‑tolerant quantum computing.
We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default CX gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.
As quantum systems expand in size and complexity, manual qubit characterization and gate optimization will be a non-scalable and time-consuming venture. Physical qubits have to be carefully calibrated because quantum processors are very sensitive to the external environment, with control hardware parameters slowly drifting during operation, affecting gate fidelity. Currently, existing calibration techniques require complex and lengthy measurements to independently control the different parameters of each gate and are unscalable to large quantum systems. Therefore, fully automated protocols with the desired functionalities are required to speed up the calibration process. This paper aims to propose single-qubit calibration of superconducting qubits under continuous weak measurements from a real physical experimental settings point of view. We propose a real-time optimal estimator of qubit states, which utilizes weak measurements and Bayesian optimization to find the optimal control pulses for gate design. Our numerical results demonstrate a significant reduction in the calibration process, obtaining a high gate fidelity. Using the proposed estimator we estimated the qubit state with and without measurement noise and the estimation error between the qubit state and the estimator state is less than 0.02. With this setup, we drive an approximated pi pulse with final fidelity of 0.9928. This shows that our proposed strategy is robust against the presence of measurement and environmental noise and can also be applicable for the calibration of many other quantum computation technologies.
Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on RZX gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking, our most modest fidelity gain was from 98.16(7)% to 99.15(3)% for the application of two RZX(π/2) gates with one shared qubit. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
Designing a qubit architecture is one of the most critical challenges in achieving scalable and fault-tolerant quantum computing as the performance of a quantum computer is heavily dependent on the coherence times, connectivity and low noise environments. Superconducting qubits have emerged as a frontrunner among many competing technologies, primarily because of their speed of operations, relatively well-developed and offer a promising path toward scalability. Here, we address the challenges of optimizing superconducting qubit hardware through the development of a comprehensive theoretical framework that spans the entire process - from design to the calibration of hardware through quantum gate execution. We develop this framework in four key steps: circuit design, electromagnetic analysis, spectral analysis, and pulse sequencing with calibration. We first refine the qubit's core components - such as capacitance, Josephson junctions, and resonators - to set the foundation for strong performance. The electromagnetic analysis, using the Lumped Oscillator model, allows us to map out the capacitance matrix, ensuring that we minimize spectral dispersion while maximizing coherence times. Following this, we conduct spectral analysis to fine-tune the qubit's frequency spectrum and coherence properties, ensuring that the qubit parameters are optimized. Finally, we focus on pulse sequencing, including pulse-width optimization, DRAG optimization, and randomized benchmarking, to achieve high gate fidelity. We applied this framework to both Transmon and Fluxonium qubits, obtaining results that closely match those found in experimental studies. This work provides a detailed and practical approach to the design, optimization, and calibration of superconducting qubits, contributing to the broader effort to develop scalable quantum computing technologies.