Fault tolerance is crucial for enabling large-scale quantum computations, with surface codes emerging as prominent error correction techniques due to their high error threshold and reliance on nearest-neighbor interactions. Despite the advantages of surface codes, they demand a substantial number of qubits to encode a single logical qubit, making them resource-intensive. Two primary approaches exist to encode multiple logical qubits: patch-based and defect-based. This study focuses on the latter approach, which involves creating holes in the surface code for logical qubit encoding. With the defect-based approach, we need to account for trade-offs between the number of logical qubits and the logical error rates, so we employ an optimization algorithm to evaluate the maximum number of logical qubits for a given error rate. Through a series of experiments, we assess the limitations of the defect-based approach and investigate the impact of various hole types on logical qubit encoding.
Fault tolerance is crucial for enabling large-scale quantum computations, with surface codes emerging as prominent error correction techniques due to their high error threshold and reliance on nearest-neighbor interactions. Despite the advantages of surface codes, they demand a substantial number of qubits to encode a single logical qubit, making them resource-intensive. Two primary approaches exist to encode multiple logical qubits: patch-based and defect-based. This study focuses on the latter approach, which involves creating holes in the surface code for logical qubit encoding. With the defect-based approach, we need to account for trade-offs between the number of logical qubits and the logical error rates, so we employ an optimization algorithm to evaluate the maximum number of logical qubits for a given error rate. Through a series of experiments, we assess the limitations of the defect-based approach and investigate the impact of various hole types on logical qubit encoding.
As its parallel processing ability, quantum computing has an exponential acceleration over classical computing. However, quantum systems are fragile and susceptible to noise. Quantum error correction code is an effective means to overcome quantum noise. Quantum surface codes are topologically stable subcodes that have great potential for large-scale fault-tolerant quantum computing because of their structural nearest neighbor characteristics and high fault-tolerance thresholds. The existing boundary-based surface codes can encode one logical qubit. This paper mainly studies how to implement multi-logical-qubits encoding based on the boundary, including designing the structure of the surface code, finding out the corresponding stabilizers and logical operations according to the structure, and further designing the coding circuit based on the stabilizers. After research on the single qubit CNOT implementation principle based on measurement and correcting and the logic CNOT implementation based on fusion and segmentation, we further optimized implementation scheme of the logic CNOT implementation based on fusion and segmentation. The scheme is extended to the designed multi-logical-qubits surface code to realize the CNOT operation between the multi-logical-qubits surface codes, and the correctness of the quantum circuit is verified by simulation. The multi-logical-qubits surface code designed in this paper overcomes the disadvantage that the single-logical-qubit surface code can not be densely embedded in the quantum chip, improves the length of some logical operations, and increases the fault tolerance ability. The idea of joint measurement reduces the requirement for ancilla qubits and reduces the demand for quantum resources in the implementation process.
Fault-tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes that encode logical qubits across many physical qubits to detect and correct errors. The surface code is among the most widely studied codes due to its high error threshold, the existence of efficient decoders, and hardware-friendly properties: a planar, two-dimensional layout with nearest-neighbor connectivity. In practice, however, the fabrication of solid-state quantum processors introduces hardware defects, resulting in defective qubits and couplers that must be discarded. Adapting the surface code to these defects often requires measuring the X- and Z-type checks in separate rounds rather than simultaneously. In this work, we investigate the optimal X-to-Z checks round-scheduling ratio under biased noise systems. Our results characterize how key architectural parameters, such as noise bias, code distance, and defect rate, impact the logical error rate. We provide insights into how to determine the optimal scheduling ratio directly from device calibration data, enabling manufacturers to maximize performance without extensive simulations. Our approach reduces the logical error rate by up to 4.25× at a 1% defect rate and up to 8.46× at a 2% defect rate for a distance-13 surface code under moderately biased noise. Furthermore, we demonstrate that the benefits of round-scheduling extend beyond the defective-hardware setting. In biased-noise architectures subject to CNOT crosstalk, separating X and Z measurement rounds yields up to 4.5× reduction in logical error rate.
The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits.Here, we present surface code error-correction schemes using only Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).
Whether it is at the fabrication stage or during the course of the quantum computation, e.g. because of high-energy events like cosmic rays, the qubits constituting an error correcting code may be rendered inoperable. Such defects may correspond to individual qubits or to clusters and could potentially disrupt the code sufficiently to generate logical errors. In this paper, we explore a novel a d a p t i v e approach for surface code quantum error correction on a defective lattice. We show that combining an appropriate defect detection algorithm and a quarantine of the identified zone allows one to preserve the advantage of quantum error correction at finite code sizes, at the cost of a qubit overhead that scales with the size of the defect. Our numerics indicate that the code's threshold need not be significantly affected; for example, for a certain scenario where small defects repeatedly arise in each logical qubit, the noise threshold is 2.7 % (versus the defect-free case of 2.9 % ). These results pave the way to the experimental implementation of large-scale quantum computers where defects will be inevitable.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.