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arXiv:2608.05518

X-Z Round Scheduling for the Surface Code with Defects under Biased Noise

Lakshika Rathi, Pau Escofet, Joshua Viszlai, Margaret Martonosi

quant-phSubmitted Aug 6, 2026• Announced Aug 7, 2026• 0 citations
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Abstract

Fault-tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes that encode logical qubits across many physical qubits to detect and correct errors. The surface code is among the most widely studied codes due to its high error threshold, the existence of efficient decoders, and hardware-friendly properties: a planar, two-dimensional layout with nearest-neighbor connectivity. In practice, however, the fabrication of solid-state quantum processors introduces hardware defects, resulting in defective qubits and couplers that must be discarded. Adapting the surface code to these defects often requires measuring the $X$- and $Z$-type checks in separate rounds rather than simultaneously. In this work, we investigate the optimal $X$-to-$Z$ checks round-scheduling ratio under biased noise systems. Our results characterize how key architectural parameters, such as noise bias, code distance, and defect rate, impact the logical error rate. We provide insights into how to determine the optimal scheduling ratio directly from device calibration data, enabling manufacturers to maximize performance without extensive simulations. Our approach reduces the logical error rate by up to $4.25\times$ at a $1\%$ defect rate and up to $8.46\times$ at a $2\%$ defect rate for a distance-$13$ surface code under moderately biased noise. Furthermore, we demonstrate that the benefits of round-scheduling extend beyond the defective-hardware setting. In biased-noise architectures subject to CNOT crosstalk, separating $X$ and $Z$ measurement rounds yields up to $4.5\times$ reduction in logical error rate.

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A solid-state quantum-computing architecture will require the fabrication of arrays of many coupled qubits. It is inevitable that this process will produce qubits and couplers with varying performance, with some components underperforming due to imperfect fabrication. Quantum error-correction requires high-performing components and hence these defects must be dealt with, either by adapting the code to exclude the defects, or by informing the decoder to accommodate defects in post-processing. Here we implement and compare strategies to operate distance-5 surface codes on a quantum processor consisting of a square-lattice array of 120 superconducting qubits. We demonstrate a dramatic reduction in the probability of a logical error in a memory experiment by excluding underperforming components, compared with both a standard approach of ignoring defects, and a defect-aware decoding approach. We observe up to 2.8X improvement in logical errors per round when excluding defects compared with the standard defect-ignorant approach (1.62% compared to 4.49%). In contrast, defect-aware decoding gives only modest gains. Defects are also expected to be particularly harmful for measurement-based logical operations. Using a stability experiment we show that excluding defects resurrects measurement-based logic gate performance, observing a 6.3% per-round suppression of failure rate when excluding defects, compared to zero suppression otherwise. Furthermore, we show a further substantial decrease in logical errors when using leakage post-selection in combination with our defect exclusion strategies, resulting in a distance-5 code outperforming the best distance-3 in one basis. Our experiments therefore give a proof-of-principle demonstration of the essential utility of defect exclusion methods in the scale-up of solid-state quantum computing approaches.

quant-pharXiv:2607.12118•Jul 15, 2026•0 citations

Tailoring surface codes: Improvements in quantum error correction with biased noise

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For quantum computers to reach their full potential will require error correction. We study the surface code, one of the most promising quantum error correcting codes, in the context of predominantly dephasing (Z-biased) noise, as found in many quantum architectures. We find that the surface code is highly resilient to Y-biased noise, and tailor it to Z-biased noise, whilst retaining its practical features. We demonstrate ultrahigh thresholds for the tailored surface code: ~39% with a realistic bias of  = 100, and ~50% with pure Z noise, far exceeding known thresholds for the standard surface code: ~11% with pure Z noise, and ~19% with depolarizing noise. Furthermore, we provide strong evidence that the threshold of the tailored surface code tracks the hashing bound for all biases. We reveal the hidden structure of the tailored surface code with pure Z noise that is responsible for these ultrahigh thresholds. As a consequence, we prove that its threshold with pure Z noise is 50%, and we show that its distance to Z errors, and the number of failure modes, can be tuned by modifying its boundary. For codes with appropriately modified boundaries, the distance to Z errors is O(n) compared to O(n1/2) for square codes, where n is the number of physical qubits. We demonstrate that these characteristics yield a significant improvement in logical error rate with pure Z and Z-biased noise. Finally, we introduce an efficient approach to decoding that exploits code symmetries with respect to a given noise model, and extends readily to the fault-tolerant context, where measurements are unreliable. We use this approach to define a decoder for the tailored surface code with Z-biased noise. Although the decoder is suboptimal, we observe exceptionally high fault-tolerant thresholds of ~5% with bias  = 100 and exceeding 6% with pure Z noise. Our results open up many avenues of research and, recent developments in bias-preserving gates, highlight their direct relevance to experiment.

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Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.

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Synchronization for Fault-Tolerant Quantum Computers

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Quantum Error Correction (QEC) codes store information reliably in logical qubits by encoding them in a larger number of less reliable qubits.The surface code, known for its high resilience to physical errors, is a leading candidate for fault-tolerant quantum computing (FTQC).Logical qubits encoded with the surface code can be in different phases of their syndrome generation cycle, thereby introducing desynchronization in the system.This can occur due to the production of non-Clifford states, dropouts due to fabrication defects, and the use of other QEC codes with the surface code to reduce resource requirements.Logical operations require the syndrome generation cycles of the logical qubits involved to be synchronized.This requires the leading qubit to pause or slow down its cycle, allowing more errors to accumulate before the next cycle, thereby increasing the risk of uncorrectable errors.To synchronize the syndrome generation cycles of logical qubits, we define three policies -Passive, Active, and Hybrid.The Passive policy is the baseline, and the simplest, wherein the leading logical qubits idle until they are synchronized with the remaining logical qubits.On the other hand, the Active policy aims to slow the leading logical qubits down gradually, by inserting short idle periods before multiple code cycles.This approach reduces the logical error rate (LER) by up to 2.4× compared to the Passive policy.The Hybrid policy further reduces the LER by up to 3.4× by reducing the synchronization slack and running a few additional rounds of error correction.Furthermore, the reduction in the logical error rate with the proposed synchronization policies enables a speedup in decoding latency of up to 2.2× with a circuit-level noise model.

arXiv:2506.10258•Proceedings - International Symposium on Computer Architecture/Proceedings•Jun 20, 2025•4 citations

Design and Analysis of Planar Surface and Perfect Quantum Error Correction Codes

Mayasa Al-Hinai, Hafiz M. Asif

Quantum Error Correction (QEC) is essential for achieving fault-tolerant quantum computation, enabling the protection of fragile quantum information from decoherence and noise. While classical Forward Error Correction (FEC) codes have been highly effective in digital communication systems, their direct application to quantum systems is inadequate mainly due to the no cloning theorem and the continuous nature of quantum errors. Unlike classical FECs, QEC is designed to detect and correct both bit-flip and phase-flip errors without disturbing the encoded quantum state. This paper presents the code structure design and simulation of two quantum error correction codes—the Planar surface code and the 5-qubit Perfect code—using Qiskit and Stim on Google Colab. It is worth mentioning here that the performance of the Steane [ [7], [1], [3]] code is included in the current work as a benchmark. The codes are evaluated under statistical noise models, including amplitude damping and dephasing, which closely mirror the physical behavior of quantum hardware. The primary performance metric, for performance assessment, is the logical error rate, evaluated across a range of physical error rates and code distances under each noise model. The simulation results show that increasing the distance of the Planar code significantly reduces the logical error rates, demonstrating superior performance compared to other similar codes under this study.

IEEE Asia Pacific Conference on Wireless and Mobile (APWiMob)•Nov 6, 2025•0 citations

Developing and Analyzing the Defect-Based Surface Codes Using Optimization Algorithms

Samira Sayedsalehi, Nader Bagherzadeh, Alberto Antonio Del Barrio +2 more

Fault tolerance is crucial for enabling large-scale quantum computations, with surface codes emerging as prominent error correction techniques due to their high error threshold and reliance on nearest-neighbor interactions. Despite the advantages of surface codes, they demand a substantial number of qubits to encode a single logical qubit, making them resource-intensive. Two primary approaches exist to encode multiple logical qubits: patch-based and defect-based. This study focuses on the latter approach, which involves creating holes in the surface code for logical qubit encoding. With the defect-based approach, we need to account for trade-offs between the number of logical qubits and the logical error rates, so we employ an optimization algorithm to evaluate the maximum number of logical qubits for a given error rate. Through a series of experiments, we assess the limitations of the defect-based approach and investigate the impact of various hole types on logical qubit encoding.

Quantum Reports•May 31, 2025•1 citation
Fault-tolerant Quantum Computing (FTQC) relies on Quantum Error Correction (QEC) codes that encode logical qubits across many physical qubits to detect and correct errors. The surface code is among the most widely studied codes due to its high error threshold, the existence of efficient decoders, and hardware-friendly properties: a planar, two-dimensional layout with nearest-neighbor connectivity. In practice, however, the fabrication of solid-state quantum processors introduces hardware defects, resulting in defective qubits and couplers that must be discarded. Adapting the surface code to these defects often requires measuring the XXX- and ZZZ-type checks in separate rounds rather than simultaneously. In this work, we investigate the optimal XXX-to-ZZZ checks round-scheduling ratio under biased noise systems. Our results characterize how key architectural parameters, such as noise bias, code distance, and defect rate, impact the logical error rate. We provide insights into how to determine the optimal scheduling ratio directly from device calibration data, enabling manufacturers to maximize performance without extensive simulations. Our approach reduces the logical error rate by up to 4.25×4.25\times4.25× at a 1%1\%1% defect rate and up to 8.46×8.46\times8.46× at a 2%2\%2% defect rate for a distance-131313 surface code under moderately biased noise. Furthermore, we demonstrate that the benefits of round-scheduling extend beyond the defective-hardware setting. In biased-noise architectures subject to CNOT crosstalk, separating XXX and ZZZ measurement rounds yields up to 4.5×4.5\times4.5× reduction in logical error rate.
A solid-state quantum-computing architecture will require the fabrication of arrays of many coupled qubits. It is inevitable that this process will produce qubits and couplers with varying performance, with some components underperforming due to imperfect fabrication. Quantum error-correction requires high-performing components and hence these defects must be dealt with, either by adapting the code to exclude the defects, or by informing the decoder to accommodate defects in post-processing. Here we implement and compare strategies to operate distance-5 surface codes on a quantum processor consisting of a square-lattice array of 120 superconducting qubits. We demonstrate a dramatic reduction in the probability of a logical error in a memory experiment by excluding underperforming components, compared with both a standard approach of ignoring defects, and a defect-aware decoding approach. We observe up to 2.8X improvement in logical errors per round when excluding defects compared with the standard defect-ignorant approach (1.62% compared to 4.49%). In contrast, defect-aware decoding gives only modest gains. Defects are also expected to be particularly harmful for measurement-based logical operations. Using a stability experiment we show that excluding defects resurrects measurement-based logic gate performance, observing a 6.3% per-round suppression of failure rate when excluding defects, compared to zero suppression otherwise. Furthermore, we show a further substantial decrease in logical errors when using leakage post-selection in combination with our defect exclusion strategies, resulting in a distance-5 code outperforming the best distance-3 in one basis. Our experiments therefore give a proof-of-principle demonstration of the essential utility of defect exclusion methods in the scale-up of solid-state quantum computing approaches.
For quantum computers to reach their full potential will require error correction. We study the surface code, one of the most promising quantum error correcting codes, in the context of predominantly dephasing (Z-biased) noise, as found in many quantum architectures. We find that the surface code is highly resilient to Y-biased noise, and tailor it to Z-biased noise, whilst retaining its practical features. We demonstrate ultrahigh thresholds for the tailored surface code: ~39% with a realistic bias of  = 100, and ~50% with pure Z noise, far exceeding known thresholds for the standard surface code: ~11% with pure Z noise, and ~19% with depolarizing noise. Furthermore, we provide strong evidence that the threshold of the tailored surface code tracks the hashing bound for all biases. We reveal the hidden structure of the tailored surface code with pure Z noise that is responsible for these ultrahigh thresholds. As a consequence, we prove that its threshold with pure Z noise is 50%, and we show that its distance to Z errors, and the number of failure modes, can be tuned by modifying its boundary. For codes with appropriately modified boundaries, the distance to Z errors is O(n) compared to O(n1/2) for square codes, where n is the number of physical qubits. We demonstrate that these characteristics yield a significant improvement in logical error rate with pure Z and Z-biased noise. Finally, we introduce an efficient approach to decoding that exploits code symmetries with respect to a given noise model, and extends readily to the fault-tolerant context, where measurements are unreliable. We use this approach to define a decoder for the tailored surface code with Z-biased noise. Although the decoder is suboptimal, we observe exceptionally high fault-tolerant thresholds of ~5% with bias  = 100 and exceeding 6% with pure Z noise. Our results open up many avenues of research and, recent developments in bias-preserving gates, highlight their direct relevance to experiment.
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.
Quantum Error Correction (QEC) codes store information reliably in logical qubits by encoding them in a larger number of less reliable qubits.The surface code, known for its high resilience to physical errors, is a leading candidate for fault-tolerant quantum computing (FTQC).Logical qubits encoded with the surface code can be in different phases of their syndrome generation cycle, thereby introducing desynchronization in the system.This can occur due to the production of non-Clifford states, dropouts due to fabrication defects, and the use of other QEC codes with the surface code to reduce resource requirements.Logical operations require the syndrome generation cycles of the logical qubits involved to be synchronized.This requires the leading qubit to pause or slow down its cycle, allowing more errors to accumulate before the next cycle, thereby increasing the risk of uncorrectable errors.To synchronize the syndrome generation cycles of logical qubits, we define three policies -Passive, Active, and Hybrid.The Passive policy is the baseline, and the simplest, wherein the leading logical qubits idle until they are synchronized with the remaining logical qubits.On the other hand, the Active policy aims to slow the leading logical qubits down gradually, by inserting short idle periods before multiple code cycles.This approach reduces the logical error rate (LER) by up to 2.4× compared to the Passive policy.The Hybrid policy further reduces the LER by up to 3.4× by reducing the synchronization slack and running a few additional rounds of error correction.Furthermore, the reduction in the logical error rate with the proposed synchronization policies enables a speedup in decoding latency of up to 2.2× with a circuit-level noise model.
Quantum Error Correction (QEC) is essential for achieving fault-tolerant quantum computation, enabling the protection of fragile quantum information from decoherence and noise. While classical Forward Error Correction (FEC) codes have been highly effective in digital communication systems, their direct application to quantum systems is inadequate mainly due to the no cloning theorem and the continuous nature of quantum errors. Unlike classical FECs, QEC is designed to detect and correct both bit-flip and phase-flip errors without disturbing the encoded quantum state. This paper presents the code structure design and simulation of two quantum error correction codes—the Planar surface code and the 5-qubit Perfect code—using Qiskit and Stim on Google Colab. It is worth mentioning here that the performance of the Steane [ [7], [1], [3]] code is included in the current work as a benchmark. The codes are evaluated under statistical noise models, including amplitude damping and dephasing, which closely mirror the physical behavior of quantum hardware. The primary performance metric, for performance assessment, is the logical error rate, evaluated across a range of physical error rates and code distances under each noise model. The simulation results show that increasing the distance of the Planar code significantly reduces the logical error rates, demonstrating superior performance compared to other similar codes under this study.
Fault tolerance is crucial for enabling large-scale quantum computations, with surface codes emerging as prominent error correction techniques due to their high error threshold and reliance on nearest-neighbor interactions. Despite the advantages of surface codes, they demand a substantial number of qubits to encode a single logical qubit, making them resource-intensive. Two primary approaches exist to encode multiple logical qubits: patch-based and defect-based. This study focuses on the latter approach, which involves creating holes in the surface code for logical qubit encoding. With the defect-based approach, we need to account for trade-offs between the number of logical qubits and the logical error rates, so we employ an optimization algorithm to evaluate the maximum number of logical qubits for a given error rate. Through a series of experiments, we assess the limitations of the defect-based approach and investigate the impact of various hole types on logical qubit encoding.