The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits.Here, we present surface code error-correction schemes using only Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.
The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits.Here, we present surface code error-correction schemes using only Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.
We devise a new realization of the surface code on a rectangular lattice of qubits utilizing single-qubit and nearest-neighbor two-qubit Pauli measurements and three auxiliary qubits per plaquette. This realization gains substantial advantages over prior pairwise measurement-based realizations of the surface code. It has a short operation period of 4 steps and our performance analysis for a standard circuit noise model yields a high fault-tolerance threshold of approximately 0.66 % . The syndrome extraction circuits avoid bidirectional hook errors, so we can achieve full code distance by choosing appropriate boundary conditions. We also construct variants of the syndrome extraction circuits that entirely prevent hook errors, at the cost of larger circuit depth. This achieves full distance regardless of boundary conditions, with only a modest decrease in the threshold. Furthermore, we propose an efficient strategy for dealing with dead components (qubits and measurements) in our surface code realization, which can be adopted more generally for other surface code realizations. This new surface code realization is highly optimized for Majorana-based hardware, accounting for constraints imposed by layouts and the implementation of measurements, making it competitive with the recently proposed Floquet codes.
As its parallel processing ability, quantum computing has an exponential acceleration over classical computing. However, quantum systems are fragile and susceptible to noise. Quantum error correction code is an effective means to overcome quantum noise. Quantum surface codes are topologically stable subcodes that have great potential for large-scale fault-tolerant quantum computing because of their structural nearest neighbor characteristics and high fault-tolerance thresholds. The existing boundary-based surface codes can encode one logical qubit. This paper mainly studies how to implement multi-logical-qubits encoding based on the boundary, including designing the structure of the surface code, finding out the corresponding stabilizers and logical operations according to the structure, and further designing the coding circuit based on the stabilizers. After research on the single qubit CNOT implementation principle based on measurement and correcting and the logic CNOT implementation based on fusion and segmentation, we further optimized implementation scheme of the logic CNOT implementation based on fusion and segmentation. The scheme is extended to the designed multi-logical-qubits surface code to realize the CNOT operation between the multi-logical-qubits surface codes, and the correctness of the quantum circuit is verified by simulation. The multi-logical-qubits surface code designed in this paper overcomes the disadvantage that the single-logical-qubit surface code can not be densely embedded in the quantum chip, improves the length of some logical operations, and increases the fault tolerance ability. The idea of joint measurement reduces the requirement for ancilla qubits and reduces the demand for quantum resources in the implementation process.
High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.
Quantum error correction is crucial for any quantum computing platform to achieve truly scalable quantum computation.The surface code and its variants have been considered the most promising quantum error correction scheme due to their high threshold, low overhead, and relatively simple structure that can naturally be implemented in many existing qubit architectures, such as superconducting qubits.The recent development of Floquet codes by Hastings and Haah offers another promising approach.By going beyond the usual paradigm of stabilizer codes, Floquet codes achieve similar performance while being constructed entirely from two-qubit measurements.This makes them particularly suitable for platforms where two-qubit measurements can be implemented directly, such as the measurement-only topological qubits based on Majorana zero modes (MZMs) proposed by Karzig et al.Here, we explain how two variants of Floquet codes can be implemented on MZM-based architectures without any auxiliary qubits for syndrome measurement and with shallow syndrome-extraction sequences.We then numerically demonstrate their favorable performance.In particular, we show that they improve the threshold for scalable quantum computation in MZM-based systems by an order of magnitude and significantly reduce space and time overheads below threshold.
Fault tolerance is crucial for enabling large-scale quantum computations, with surface codes emerging as prominent error correction techniques due to their high error threshold and reliance on nearest-neighbor interactions. Despite the advantages of surface codes, they demand a substantial number of qubits to encode a single logical qubit, making them resource-intensive. Two primary approaches exist to encode multiple logical qubits: patch-based and defect-based. This study focuses on the latter approach, which involves creating holes in the surface code for logical qubit encoding. With the defect-based approach, we need to account for trade-offs between the number of logical qubits and the logical error rates, so we employ an optimization algorithm to evaluate the maximum number of logical qubits for a given error rate. Through a series of experiments, we assess the limitations of the defect-based approach and investigate the impact of various hole types on logical qubit encoding.
Realizing practical quantum computers requires quantum error correction, but the most widely implemented approach, the planar surface code, demands a substantial physical qubit overhead. Here, we demonstrate that partitioning quantum processors into manageable, flat modules with non-local inter-module connections provides a natural solution. By wiring sparse, static boundary connections between Euclidean planar modules, we construct modular hyperbolic surface and color codes, based on new families of semi-hyperbolic codes. Using modular syndrome extraction circuits and efficient neural network and matching decoders, our circuit-level simulations show that this modular memory design can reduce the physical qubit overhead by tenfold or more compared to the surface code, even under elevated inter-module seam error rates. Projecting to larger system sizes, we find modular codes with encoding rate k/n=1/16 and distance d≥22, exceeding both the rate and distance of the [[288,12,18]] two-gross bivariate bicycle code while using mostly nearest-neighbor gates within planar modules, and implying an over 30× overhead reduction relative to surface codes. We develop fault-tolerant walking circuits for implementing logic via code automorphisms, which we co-design with low-weight, highly symmetrical logical bases and a modular extractor system that is ≈4.5× smaller than the code itself. Combining these methods, our modular memory can be used as dense storage in a universal fault-tolerant architecture, unlocking the efficiency of high-rate codes without sacrificing the fabrication advantages of planar modules.