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arXiv:2610.03682

Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules

Oscar Higgott, Hasan Sayginel, Francisco J. H. Heras, Zhiyang He, Tomas Jochym-O'Connor, Andrew W. Senior, Lei M. Zhang, Thomas Edlich, James S. Spencer, Matt McEwen, Craig Gidney, Johannes Bausch, Pushmeet Kohli, Hartmut Neven

quant-phSubmitted Oct 2, 2026• Announced Oct 5, 2026• 0 citations
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Abstract

Realizing practical quantum computers requires quantum error correction, but the most widely implemented approach, the planar surface code, demands a substantial physical qubit overhead. Here, we demonstrate that partitioning quantum processors into manageable, flat modules with non-local inter-module connections provides a natural solution. By wiring sparse, static boundary connections between Euclidean planar modules, we construct modular hyperbolic surface and color codes, based on new families of semi-hyperbolic codes. Using modular syndrome extraction circuits and efficient neural network and matching decoders, our circuit-level simulations show that this modular memory design can reduce the physical qubit overhead by tenfold or more compared to the surface code, even under elevated inter-module seam error rates. Projecting to larger system sizes, we find modular codes with encoding rate $k/n=1/16$ and distance $d\geq 22$, exceeding both the rate and distance of the $[[288,12,18]]$ two-gross bivariate bicycle code while using mostly nearest-neighbor gates within planar modules, and implying an over $30\times$ overhead reduction relative to surface codes. We develop fault-tolerant walking circuits for implementing logic via code automorphisms, which we co-design with low-weight, highly symmetrical logical bases and a modular extractor system that is $\approx 4.5\times$ smaller than the code itself. Combining these methods, our modular memory can be used as dense storage in a universal fault-tolerant architecture, unlocking the efficiency of high-rate codes without sacrificing the fabrication advantages of planar modules.

Comments
112 pages, 73 figures, 20 tables (19 pages main text and Methods; 93 pages Supplementary Information)

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Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules: A Reconciled Quantitative Assessment

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The planar surface code protects quantum information robustly but pays for its two-dimensional layout with an encoding rate that vanishes as the distance grows, so fault-tolerant memories require hundreds to thousands of physical qubits per logical qubit. A recent proposal constructs modular hyperbolic surface and color codes by partitioning a quantum processor into flat Euclidean modules and wiring sparse, static boundary connections between them, yielding semi-hyperbolic codes with constant encoding rate [1,4]. In this paper we provide an independent, fully explicit quantitative analysis of that proposal. Taking the reported parameters — encoding rate $k/n = 1/16$ and distance $d \geq 22$ — as inputs, we compute that a twelve-logical-qubit modular memory requires $n_{\mathrm{mod}} = 192$ physical qubits, versus $11100$ data qubits for twelve distance-$22$ rotated surface-code patches, a raw overhead reduction of $57.8\times$; the reduction remains $\geq 30\times$ even if the true modular implementation uses up to $370$ physical qubits. We further develop a seam-noise mixture model and compute the seam-error budget under which the modular advantage survives: with a seam fraction $f = 0.1443$, seam links may carry up to $\gamma \approx 2.5\times$ the intra-module error rate before a tenfold advantage at matched distance is exhausted. We compare against the $[[288,12,18]]$ bivariate bicycle code ($1.5\times$ fewer qubits for the modular code, at strictly larger distance) and situate the proposal within the low-overhead QEC landscape. All arithmetic is shown step by step; all projections are labeled with stated assumptions. ## 1. Introduction Quantum error correction (QEC) is the accepted route to fault-tolerant quantum computation, but the leading practical scheme — the planar surface code — has an encoding rate $k/n$ that tends to zero as the code distance $d$ grows. For a target logical error rate, the required physical-to-logical qubit ratio grows roughly quadra Full text and updates: papers.qnfo.org/papers/low-overhead-quantum-error-correction-with-boundary-connected-planar-modules-a-r/

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Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.

quant-pharXiv:2605.04663•May 7, 2026•0 citations

Quantum error correction at ultra-low overhead

Zhide Lu, Weikang Li, Dong-Ling Deng

Suppressing errors is the central challenge for useful large-scale quantum computing. While quantum error correction promises a viable solution to this challenge, existing codes typically suffer from trade-offs among encoding efficiency, error threshold, and hardware feasibility. Here, we introduce Cornucopia codes, a family of practical, hardware-efficient quantum low-density parity-check codes that achieve an ultra-high encoding rate exceeding $1/2$ while maintaining a pseudo-threshold exceeding $0.4\%$ under the standard circuit-level noise model. Inspired by recent affine-permutation-based code constructions and the long-range connectivity available in reconfigurable neutral-atom arrays, we adopt a structured code geometry in which the code layout, atom rearrangement, and syndrome-extraction schedule are co-designed. This structure enables nonlocal syndrome measurements through simple, parallel atom rearrangements. A complete syndrome extraction cycle measures all $X$- and $Z$-type checks in parallel with $12$ entangling layers, independent of the code size. The resulting threshold is comparable to those of the surface code and bivariate bicycle codes. In particular, a single code block $[[2844,1426,18]]$ encodes $1{,}426$ distance-$18$ logical qubits, achieving an extrapolated logical error rate of $2.6\times10^{-16}$ ($1.9\times10^{-31}$) per logical qubit per cycle, assuming the physical error rate of $0.1\%$ ($0.01\%$). By comparison, a bivariate bicycle code implementation would require more than $68{,}000$ physical qubits to encode the same number of logical qubits at a comparable logical error rate. These results bring demonstrations of ultra-low-overhead quantum error correction within the reach of near-term quantum processors.

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High-threshold and low-overhead fault-tolerant quantum memory

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Abstract The accumulation of physical errors 1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction 4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm 5 . We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes 6 . Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code 7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length- n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.

arXiv:2308.07915•Nature•Mar 27, 2024•456 citations
Realizing practical quantum computers requires quantum error correction, but the most widely implemented approach, the planar surface code, demands a substantial physical qubit overhead. Here, we demonstrate that partitioning quantum processors into manageable, flat modules with non-local inter-module connections provides a natural solution. By wiring sparse, static boundary connections between Euclidean planar modules, we construct modular hyperbolic surface and color codes, based on new families of semi-hyperbolic codes. Using modular syndrome extraction circuits and efficient neural network and matching decoders, our circuit-level simulations show that this modular memory design can reduce the physical qubit overhead by tenfold or more compared to the surface code, even under elevated inter-module seam error rates. Projecting to larger system sizes, we find modular codes with encoding rate k/n=1/16k/n=1/16k/n=1/16 and distance d≥22d\geq 22d≥22, exceeding both the rate and distance of the [[288,12,18]][[288,12,18]][[288,12,18]] two-gross bivariate bicycle code while using mostly nearest-neighbor gates within planar modules, and implying an over 30×30\times30× overhead reduction relative to surface codes. We develop fault-tolerant walking circuits for implementing logic via code automorphisms, which we co-design with low-weight, highly symmetrical logical bases and a modular extractor system that is ≈4.5×\approx 4.5\times≈4.5× smaller than the code itself. Combining these methods, our modular memory can be used as dense storage in a universal fault-tolerant architecture, unlocking the efficiency of high-rate codes without sacrificing the fabrication advantages of planar modules.
Quantum fault tolerance is a prerequisite to harness the full potential of quantum computers. However, achieving fault tolerance remains a major challenge since it requires optimizing tradeoffs between several intertwined theoretical and experimental parameters, including the encoding rate, code distance, parity-check weights, code planarity, and routing. Surface codes remain strong candidates for fault tolerance due to their simple geometric structure, established decoding methods, locality, and experimental attainability. In this work, we present finite families of hyperbolic surface codes that leverage the optimal efficiency scaling kd2/n=C(log⁡k)2kd^2/n = C (\log{k})^2kd2/n=C(logk)2 attainable by surface codes with bounded local geometry. We show that optimizing the periodic identifications can double the code distance and thereby increase the code's efficiency by a factor of four, at fixed qubit count, encoding rate, and parity-check weight. We also address the routing problem of hyperbolic surface codes by introducing a topology-aware algorithm that partitions a hyperbolic code into bounded planar modules while reducing long-range communications demand. Circuit-level Monte Carlo simulations yield finite-size threshold estimates for both modular and monolithic layouts, showing that tripling the long-range gate error probability mildly lowers, but does not eliminate, the estimated error-correction thresholds. Together, these results strengthen the case for hyperbolic surface codes as structured and highly efficient large-scale quantum error correction codes for future fault-tolerant architectures.
The planar surface code protects quantum information robustly but pays for its two-dimensional layout with an encoding rate that vanishes as the distance grows, so fault-tolerant memories require hundreds to thousands of physical qubits per logical qubit. A recent proposal constructs modular hyperbolic surface and color codes by partitioning a quantum processor into flat Euclidean modules and wiring sparse, static boundary connections between them, yielding semi-hyperbolic codes with constant encoding rate [1,4]. In this paper we provide an independent, fully explicit quantitative analysis of that proposal. Taking the reported parameters — encoding rate k/n=1/16k/n = 1/16k/n=1/16 and distance d≥22d \geq 22d≥22 — as inputs, we compute that a twelve-logical-qubit modular memory requires nmod=192n_{\mathrm{mod}} = 192nmod​=192 physical qubits, versus 111001110011100 data qubits for twelve distance-222222 rotated surface-code patches, a raw overhead reduction of 57.8×57.8\times57.8×; the reduction remains ≥30×\geq 30\times≥30× even if the true modular implementation uses up to 370370370 physical qubits. We further develop a seam-noise mixture model and compute the seam-error budget under which the modular advantage survives: with a seam fraction f=0.1443f = 0.1443f=0.1443, seam links may carry up to γ≈2.5×\gamma \approx 2.5\timesγ≈2.5× the intra-module error rate before a tenfold advantage at matched distance is exhausted. We compare against the [[288,12,18]][[288,12,18]][[288,12,18]] bivariate bicycle code (1.5×1.5\times1.5× fewer qubits for the modular code, at strictly larger distance) and situate the proposal within the low-overhead QEC landscape. All arithmetic is shown step by step; all projections are labeled with stated assumptions. ## 1. Introduction Quantum error correction (QEC) is the accepted route to fault-tolerant quantum computation, but the leading practical scheme — the planar surface code — has an encoding rate k/nk/nk/n that tends to zero as the code distance ddd grows. For a target logical error rate, the required physical-to-logical qubit ratio grows roughly quadra Full text and updates: papers.qnfo.org/papers/low-overhead-quantum-error-correction-with-boundary-connected-planar-modules-a-r/
High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.
Quantum low density parity check (qLDPC) codes, particularly bivariate bicycle (BB) codes, achieve competitive fault tolerance thresholds while offering substantially higher encoding rates than planar surface codes. However, their intrinsically long-range stabilizer structure makes them difficult to implement on monolithic devices with nearest neighbor connectivity and limited qubit capacity. In this work, we study the realization of a BB code in a modular multiprocessor architecture, where quantum processors are interconnected through shared Bell pairs. We consider processors with all to all internal connectivity, which is feasible on trapped ion and neutral atom platforms, enabling flexible local gate execution while inter-processor (nonlocal) gates are mediated by shared entanglement. We describe a star network architecture that can realize this distributed setting. We partition the qubits of the [[144,12,12]] BB code across 4, 6, and 12 quantum processors and analyze the resulting logical error rates and pseudo-threshold performance under circuit level noise by varying the number of processors and a scaling factor that captures the additional noise associated with nonlocal operations. We use Monte Carlo simulations with BP+OSD decoding and extend the previously known BB code ansatz to the distributed setting. Our results provide architectural insight and design considerations for distributed BB codes in modular quantum computing architectures.
Suppressing errors is the central challenge for useful large-scale quantum computing. While quantum error correction promises a viable solution to this challenge, existing codes typically suffer from trade-offs among encoding efficiency, error threshold, and hardware feasibility. Here, we introduce Cornucopia codes, a family of practical, hardware-efficient quantum low-density parity-check codes that achieve an ultra-high encoding rate exceeding 1/21/21/2 while maintaining a pseudo-threshold exceeding 0.4%0.4\%0.4% under the standard circuit-level noise model. Inspired by recent affine-permutation-based code constructions and the long-range connectivity available in reconfigurable neutral-atom arrays, we adopt a structured code geometry in which the code layout, atom rearrangement, and syndrome-extraction schedule are co-designed. This structure enables nonlocal syndrome measurements through simple, parallel atom rearrangements. A complete syndrome extraction cycle measures all XXX- and ZZZ-type checks in parallel with 121212 entangling layers, independent of the code size. The resulting threshold is comparable to those of the surface code and bivariate bicycle codes. In particular, a single code block [[2844,1426,18]][[2844,1426,18]][[2844,1426,18]] encodes 1,4261{,}4261,426 distance-181818 logical qubits, achieving an extrapolated logical error rate of 2.6×10−162.6\times10^{-16}2.6×10−16 (1.9×10−311.9\times10^{-31}1.9×10−31) per logical qubit per cycle, assuming the physical error rate of 0.1%0.1\%0.1% (0.01%0.01\%0.01%). By comparison, a bivariate bicycle code implementation would require more than 68,00068{,}00068,000 physical qubits to encode the same number of logical qubits at a comparable logical error rate. These results bring demonstrations of ultra-low-overhead quantum error correction within the reach of near-term quantum processors.
Abstract The accumulation of physical errors 1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction 4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm 5 . We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes 6 . Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code 7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length- n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.