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Quantum Science and Technology

A flexible SoC for quantum key distribution post-processing based on RISC-V processor

Xinyi Wu, Lianye Liao, Xiaodong Fan, Ye Chen, Jinquan Huang, Minjie Liu, Zhiyu Tian, Tonglin Mu, Junran Guo, Bo Liu, Shi‐Hai Sun

Published May 13, 2025• 1 citation
Publisher

Abstract

Abstract In the domain of quantum-secure communications, post-processing emerges as a critical mechanism to ensure the security and integrity of the generated keys generated by quantum key distribution (QKD). However, existing post-processing frameworks often lack universality, being highly tailored to single-algorithm implementations and frequently neglecting key aspects such as system scalability and integration. To address these limitations, we present a novel system-on-chip (SoC) architecture for QKD post-processing, built around a co-designed framework featuring a RISC-V soft-core processor. This architecture incorporates core functionalities essential to QKD post-processing, including privacy amplification, information reconciliation, and high-speed communication interfaces. By leveraging the flexibility of the open-source RISC-V instruction set, the system achieves enhanced adaptability and energy efficiency. Additionally, a separated-bus architecture is employed, decoupling data and instruction buses to optimize data transfer efficiency and overall system performance, paving the way for scalable and high-throughput quantum communication systems. The system is deployed on the Xilinx Kintex Ultrascale series development board. At the Bob side, with a frame length of 16 384, the information reconciliation module and the privacy amplification module achieves throughputs of 29.73 Mbps and 131.07 Mbps, respectively.

DOI
10.1088/2058-9565/add801

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Abstract In the domain of quantum-secure communications, post-processing emerges as a critical mechanism to ensure the security and integrity of the generated keys generated by quantum key distribution (QKD). However, existing post-processing frameworks often lack universality, being highly tailored to single-algorithm implementations and frequently neglecting key aspects such as system scalability and integration. To address these limitations, we present a novel system-on-chip (SoC) architecture for QKD post-processing, built around a co-designed framework featuring a RISC-V soft-core processor. This architecture incorporates core functionalities essential to QKD post-processing, including privacy amplification, information reconciliation, and high-speed communication interfaces. By leveraging the flexibility of the open-source RISC-V instruction set, the system achieves enhanced adaptability and energy efficiency. Additionally, a separated-bus architecture is employed, decoupling data and instruction buses to optimize data transfer efficiency and overall system performance, paving the way for scalable and high-throughput quantum communication systems. The system is deployed on the Xilinx Kintex Ultrascale series development board. At the Bob side, with a frame length of 16 384, the information reconciliation module and the privacy amplification module achieves throughputs of 29.73 Mbps and 131.07 Mbps, respectively.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
Quantum Key Distribution (QKD) systems are a novel technology that exploits the laws of quantum mechanics to generate and distribute unconditionally secure cryptographic keys between two geographically separated parties. They are suitable for use in applications where high levels of secrecy are required, such as banking, government, and military environments. In this paper, we describe the development of a module-based QKD simulation framework that facilitates the modeling of QKD post-processing functionalities. We highlight design choices made to improve upon an initial design, which included the segmentation of functionalities associated with various phases of QKD post-processing into discrete modules implementing abstract interfaces. In addition, communication between modules was improved by implementing observers to share data, and a specific strategy for dealing with post-processing synchronization and configuration activities was designed. Collectively, these improvements resulted in a significantly enhanced analysis capability to model and study the security and performance characteristics associated with specific QKD system designs.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.
Quantum key distribution (QKD) is a promising technique for secure communication based on quantum mechanical principles. To improve the secure key rate of a QKD system, most studies on reconciliation primarily focused on improving the efficiency. With the increasing performance of QKD systems, the research priority has shifted to the improvement of both throughput and efficiency. In this paper, we propose a high performance solution of Cascade reconciliation, including a high-throughput-oriented framework and an integrated-optimization-oriented scheme. Benefiting from the fully utilizing computation and storage resources, effectively dealing with communication delays, the integrated-optimization-oriented parameters setting, etc., an excellent overall performance was achieved. Experimental results showed that, the throughput of up to 570Mbps with an efficiency of 1.038 was achieved, which, to our knowledge, was more than four times faster than any throughput previously demonstrated. Furthermore, throughputs on real data sets were capable of reaching up to 86Mbps even on embedded platforms. Additionally, our solution offers good adaptability to the fluctuating communication delay and quantum bit error rate (QBER). Based on our study, low performance (i.e. low power-consumption and cost-effective) CPU platforms will be sufficient for reconciliation in the existing and near-term QKD systems.
Key Distillation is an essential component of every quantum key distribution (QKD) system because it compensates for the inherent transmission errors of a quantum channel. However, the interoperability and throughput aspects of the post-processing components are often neglected. In this paper, we propose a high-throughput key distillation framework that supports multiple QKD protocols, implemented in a field-programmable gate array (FPGA). The proposed design adapts a MapReduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offers dynamic error correction, mutual authentication with a physically unclonable function, and an inbuilt high-speed encryption application that utilizes the key for secure communication. Additionally, we have developed a semi-automated high-level synthesis (HLS) framework that is compatible with any discrete variable QKD system, showing promising speedup. Overall, the experimental results demonstrate a noteworthy enhancement in scalability achieved through the utilization of a single FPGA platform.