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IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

FPGA Implementation of Quantum Key Distribution Post-processing for a Post-Quantum Era

S. Sivaraman, Padiraju Nagasai Aswatha, Shreoshi Chattopadhyay, Pradyumn Prabhu, Sudeendra Kumar K

Published Jun 1, 2026• 0 citations
Publisher
DOI
10.1109/vlsisata69163.2026.11610582

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Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.