Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.
Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.
Abstract Random Number Generators (RNGs) are devices whose utility spans from cryptography to gambling. Depending on the source of the random seed, RNGs are classified as Pseudo-Random Number Generators (PRNGs), which are based on mathematical algorithms, True Random Number Generators (TRNGs) sourced through seemingly random physical processes, and finally, Quantum Random Number Generators (QRNGs) which harness the intrinsic randomness of measured outcomes of quantum states. To ensure that the output of a QRNG is private and nearly uniform, the raw data undergoes a strong extraction process such as Toeplitz or Trevisan Hashing. The extraction process needs to be extremely efficient to achieve high-speed random number generation. The present work demonstrates state-of-the-art methods for performing information-theoretically provable randomness extraction using variations of the Toeplitz Hashing algorithm. These algorithms are implemented on various hardware for comprehensive analysis. Subsequently, these methods are applied to two raw data sets from a PRNG source and a quantum source. A new benchmark of 19.5 Gbps for Randomness Extraction using the Fast Fourier Transform-based Toeplitz Strong Extractor is demonstrated in this work. The implementation of the algorithm on a GPU-based system demonstrates notably enhanced speed, marking a significant leap beyond the existing state-of-the-art implementations.
As a universal-hashing function, Toeplitz hashing is migrated in QRNG from privacy amplification of QKD to execute information-theoretically provable true randomness extraction. Though random seed needed for constructing a Toeplitz matrix is longer than the output string, Toeplitz-hashing extractor is still much more favored in practical implementation of QRNG because its relative simple structure and parallel operation property compared to the other universal-hashing strong extractor, Trevisan's extractor, especially in the booming integration realization of randomness extractor via FPGA. But two origin issues have been put off for long in the random number post-processing in FPGA besides chasing speed: collision probability threaten owing to small matrix and security parameter growth due to seed reuse. In this work, seed update and collision probability are both paid close attention when realize real-time parallel post-processing of CV-QRNG, who has a pretty practical prospect as well as greatest demand on post-processing both because of whose wide detection bandwidth and multibit discretization. We propose a sub-seed generation scheme based on reading and writing between two levels of memories in FPGA, which effectively avoid the consumption of logic resources. One seeds pool is built in storage element of the FPGA and distinct random seed is chosen for each post-processing instance by a random selection process. And the seeds pool is swiftly updated via PCIe interface once security parameter reaches a pre-set threshold. Furthermore, by elaborate layout of Toeplitz matrixes and two-layer parallel pipeline algorithm with TDM designed delicately, four-channel parallel seed renewable Toeplitz post-processing with matrix of about1700×2500is realized with a real-time random number yield of 11.3 Gbps in one medium-configuration FPGA. In order to guarantee the robustness of the hardware-based parallel Toeplitz post-processing, timing is optimized by register replication, global clock buffers and data cache. This investigation fills an obvious hole in randomness extraction and provides a referential technique for privacy amplification.
Random Number Generators (RNGs) are crucial for applications ranging from cryptography to simulations. Depending on the source of randomness, RNGs are classified into Pseudo-Random Number Generators (PRNGs), True Random Number Generators (TRNGs), and Quantum Random Number Generators (QRNGs). This work presents the end-to-end development of a high-speed, high-efficiency, phase-noise-based QRNG system that taps into the quantum phase noise of a single-frequency laser, with randomness originating from spontaneous emission. Using a self-heterodyne measurement with a semiconductor laser (linewidth ≈ 5.23 GHz) operated near threshold and a $\sim$48 cm fiber delay line, a raw data generation rate of 2.0 Gbps is achieved. To ensure uniform randomness in the QRNG output, robust extraction techniques developed in-house, such as the Toeplitz Strong Extractor (TSE), are used. Randomness validation using the NIST and Diehard test suites confirms that all statistical tests pass at standard confidence levels. The developed system achieves a post-processed generation rate of 1.0 Gbps in operation and attains a Technology Readiness Level (TRL) of 7, approaching TRL 8, making it suitable for real-time secure applications such as cryptographic key generation and stochastic modeling.
Quantum random number generators (QRNG) based on continuous variable (CV) quantum fluctuations offer great potential for their advantages in measurement bandwidth, stability and integrability. More importantly, it provides an efficient and extensible path for significant promotion of QRNG generation rate. During this process, real-time randomness extraction using information theoretically secure randomness extractors is vital, because it plays critical role in the limit of throughput rate and implementation cost of QRNGs. In this work, we investigate parallel and real-time realization of several Toeplitz-hashing extractors within one field-programmable gate array (FPGA) for parallel QRNG. Elaborate layout of Toeplitz matrixes and efficient utilization of hardware computing resource in the FPGA are emphatically studied. Logic source occupation for different scale and quantity of Toeplitz matrices is analyzed and two-layer parallel pipeline algorithm is delicately designed to fully exploit the parallel algorithm advantage and hardware source of the FPGA. This work finally achieves a real-time post-processing rate of QRNG above 8 Gbps. Matching up with integrated circuit for parallel extraction of multiple quantum sideband modes of vacuum state, our demonstration shows an important step towards chip-based parallel QRNG, which could effectively improve the practicality of CV QRNGs, including device trusted, device-independent, and semi-device-independent schemes.
Quantum systems are particularly suited for generating true randomness due to their inherent unpredictability, which can be justified on physical principles. However, practical implementations of Quantum RNGs (QRNGs) are always subject to noise, or uncontrollable influences, diminishing the quality of raw randomness produced. This necessitates post-processing to convert raw output into genuine randomness. In current QRNG implementations, the critical issue of seed updating is often overlooked, risking security vulnerabilities due to increased security parameters when seeds are reused in post-processing, and frequent seed updates fail to yield net randomness, while reusing seeds relies on the assumption that the original sequence inputs are independent.In this work, we have provided a specific scheme for seed updates that balances practicality and security, exploring the parallel and real-time implementation of multiple seed real-time updating toeplitz hash extractors in an FPGA to achieve parallel QRNGs, focusing on efficient hardware computation resource use. Through logic optimization, we achieved a greater number of parallel channels and a post-processing matrix size three times larger than previous works on the same FPGA platform, utilizing fewer logic resources. This resulted in a higher rate of random number generation and enhanced security. Furthermore, with the use of higher-performance ADCs, we attained a random number production rate exceeding 20Gbps.High-speed random number transfer and seed updating were achieved using the PCIe high-speed interface.This marks a significant step toward chip-based parallel QRNGs, enhancing the practicality of CV QRNGs in trusted, device-independent, and semi-device-independent scenarios.
We present a high-speed continuous-variable quantum random number generator (QRNG) based on heterodyne detection of vacuum fluctuations. The scheme follows a source-device-independent (SDI) security model in which the entropy originates from quantum measurement uncertainty and no model of the source is required; security depends only on the trusted measurement device and the calibrated discretization, and thus remains valid even under adversarial state preparation. The optical field is split by a 90∘ optical hybrid and measured by two balanced photodiodes to obtain both quadratures of the vacuum state simultaneously. The analog outputs are digitized using a dual-channel 12-bit analog-to-digital converter operating at a sampling rate of 3.2 GS/s per channel, and processed in real time by an FPGA implementing Toeplitz hashing for randomness extraction. The quantum-to-classical noise ratio was verified through calibrated power spectral density measurements and cross-checked in the time domain, confirming vacuum-noise dominance within the 1.6 GHz detection bandwidth. After extraction, the system achieves a sustained generation rate of Rnet=33.92Gbit/s of uniformly distributed random bits, which pass all NIST and Dieharder statistical tests. The demonstrated platform provides a compact, FPGA-based realization of a practical heterodyne continuous-variable source-independent QRNG suitable for high-rate quantum communication and secure key distribution systems.