Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.
Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.
Abstract Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfections of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has several potential advantages, such as capacity to reach Shannon-limit, high IR efficiency, and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special-purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block-checked successive cancellation list (SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource utilization. Furthermore, the hardware implementation is completed based on Xilinx Zynq UltraScale+ XCZU5EV MPSoC platform and achieves an IR throughput of 15 Mbps with a block length of 212, while less than 20 % of the amount of on-chip resources are used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
Continuous-variable quantum key distribution (CV-QKD) offers an attractive route to information-theoretic secure communications using coherent detection and largely off-the-shelf telecommunication components. However, practical deployment remains constrained by the efficiency and reliability of information reconciliation in the low signal-to-noise ratio (SNR) regime, finite block-length effects, and the need to operate robustly under time-varying channels. This thesis addresses these challenges by developing short-block polar-coded reconciliation schemes, an adaptive incremental-redundancy hybrid automatic repeat request (IR-HARQ) framework tailored to CV-QKD, and a simultaneous quantum and classical communication (SQCC) architecture with joint classical--quantum optimization. Firstly, this thesis investigates polar codes as a finite-length alternative to conventional LDPC-based reconciliation. By constructing and evaluating a series of progressively enhanced reconciliation architectures, it is shown that short-block polar codes can provide improved block-error-rate (BLER) performance and higher reconciliation efficiency in the operating regime relevant to practical CV-QKD systems. The study further analyzes implementation trade-offs, including computational load distribution between Alice and Bob and the impact of decoder choices, identifying list decoding with moderate list sizes as an effective performance--complexity compromise. Secondly, to address channel variability and the sensitivity of fixed-rate reconciliation at low SNR, an IR-HARQ reconciliation protocol is proposed. Instead of committing to a single code rate, the protocol progressively reveals additional redundancy across retransmissions, effectively lowering the coding rate only when needed. A reliability-driven frozen-bit scheduling strategy is developed to maximize the error-correction benefit per disclosed bit under finite-length constraints, while ensuring that the resulting leakage is properly accounted for in privacy amplification. The proposed IR-HARQ design significantly improves reconciliation robustness and extends the achievable secure distance compared with one-shot fixed-rate baselines. Thirdly, this thesis considers SQCC, where classical data transmission and CV-QKD share the same physical link. A power-allocation model is established through the power ratio between the quantum and classical components, and the resulting classical and quantum error behaviors are characterized. By incorporating successive interference cancellation and forward error correction on both components, the proposed SQCC designs enable simultaneous classical throughput and secure key generation with controllable trade-offs among reliability, excess noise, and secret key rate. Overall, the thesis demonstrates that short-block polar coding, when combined with adaptive IR-HARQ and SQCC-aware receiver processing, provides a coherent framework for improving the practicality of CV-QKD under finite-length and time-varying conditions, thereby supporting more resource-efficient and deployable quantum-secured communication systems.
Information reconciliation (IR) ensures the correctness of quantum key distribution systems by correcting the error bits that existed in the sifted keys. In this article, we propose a polar-code-based IR scheme with the frozen-bit erasure strategy, where an equivalent transmission of sifted keys is conducted so that each frozen bit in the decoding procedure is erased to zero. Thus, our IR scheme is no longer limited by the assumption of true random numbers and can be implemented simply and efficiently. Furthermore, we implement the proposed IR scheme with the fast simplified successive-cancellation list decoder and its throughput reaches 0.68Mbps with the yield of 0.8333; when the decoder list size is 16, the block size is 1Mb and the quantum bit error rate is 0.02.
Quantum key distribution (QKD) is a promising technique for secure communication based on quantum mechanical principles. To improve the secure key rate of a QKD system, most studies on reconciliation primarily focused on improving the efficiency. With the increasing performance of QKD systems, the research priority has shifted to the improvement of both throughput and efficiency. In this paper, we propose a high performance solution of Cascade reconciliation, including a high-throughput-oriented framework and an integrated-optimization-oriented scheme. Benefiting from the fully utilizing computation and storage resources, effectively dealing with communication delays, the integrated-optimization-oriented parameters setting, etc., an excellent overall performance was achieved. Experimental results showed that, the throughput of up to 570Mbps with an efficiency of 1.038 was achieved, which, to our knowledge, was more than four times faster than any throughput previously demonstrated. Furthermore, throughputs on real data sets were capable of reaching up to 86Mbps even on embedded platforms. Additionally, our solution offers good adaptability to the fluctuating communication delay and quantum bit error rate (QBER). Based on our study, low performance (i.e. low power-consumption and cost-effective) CPU platforms will be sufficient for reconciliation in the existing and near-term QKD systems.
Quantum Key Distribution (QKD) systems will be fundamental in ensuring secure communications in future networks. However, due to device imperfections and the random nature of quantum physics itself, these systems need an information reconciliation phase to correct for errors in the key exchange. In particular, for Continuous Variable QKD (CV-QKD) systems, it is possible to employ Multi-Dimensional Reconciliation (MDR) with Quasi-Cyclic LDPC (QC-LDPC) error correction codes. To achieve good reconciliation with low SNR or to limit finite- size effects, large input block codes should be employed. FPGA acceleration is here envisioned. In this work we implemented the encoding for syndromes as large as 1Mbit with a QC-LDPC lift factor of 512 bits and achieve a throughput exceeding 3.55 Gb/s.