Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Quantum Science and Technology

The implementation of Shannon-limited polar codes-based information reconciliation for quantum key distribution

Junbin Guo, Bang-Ying Tang, Tingqin Lai, Xiaolin Liang, Siyuan Zhang, Zhiyu Tian, Jinquan Huang, Xuelin Yuan, Wanrong Yu, Bo Liu, Shaobo Luo, Shi‐Hai Sun

Published Apr 27, 2023• 7 citations
Publisher

Abstract

Abstract Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfections of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has several potential advantages, such as capacity to reach Shannon-limit, high IR efficiency, and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special-purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block-checked successive cancellation list (SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource utilization. Furthermore, the hardware implementation is completed based on Xilinx Zynq UltraScale+ XCZU5EV MPSoC platform and achieves an IR throughput of 15 Mbps with a block length of 212, while less than 20 % of the amount of on-chip resources are used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD.

DOI
10.1088/2058-9565/acd0d1

Related papers

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution

Lianye Liao, Xinyi Wu, Ye Chen +8 more

Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.

Scientific Reports•Oct 16, 2025•4 citations

Shannon-limit approached information reconciliation for quantum key distribution

Bang-Ying Tang, Bo Liu, Wanrong Yu +1 more

Abstract Information reconciliation (IR) corrects the errors in sifted keys and ensures the correctness of quantum key distribution (QKD) systems. Polar codes-based IR schemes can achieve high reconciliation efficiency; however, the incidental high frame error rate decreases the secure key rate of QKD systems. In this article, we propose a Shannon-limit approached (SLA) IR scheme, which mainly contains two phases: the forward reconciliation phase and the acknowledgment reconciliation phase. In the forward reconciliation phase, the sifted key is divided into sub-blocks and performed with the improved block checked successive cancellation list decoder of polar codes. Afterward, only the failure corrected sub-blocks perform the additional acknowledgment reconciliation phase, which decreases the frame error rate of the SLA IR scheme. The experimental results show that the overall failure probability of SLA IR scheme is decreased to $$10^{-8}$$ 10 - 8 and the efficiency is improved to 1.091 with the IR block length of 128 Mb. Furthermore, the efficiency of the proposed SLA IR scheme is 1.055, approached to Shannon limit, when the quantum bit error rate is 0.02 and the input scale of 1 Gb, which is hundred times larger than the state-of-the-art implemented polar codes-based IR schemes.

arXiv:2003.03713•Quantum Information Processing•Mar 1, 2021•21 citations

Improved reconciliation with polar codes in quantum key distribution

Sunghoon Lee, Joo Youn Park, Jun Heo

Quantum key distribution (QKD) is a cryptographic system that generates an information-theoretically secure key shared by two legitimate parties. QKD consists of two parts: quantum and classical. The latter is referred to as classical post-processing (CPP). Information reconciliation is a part of CPP in which parties are given correlated variables and attempt to eliminate the discrepancies between them while disclosing a minimum amount of information. The elegant reconciliation protocol known as \emph{Cascade} was developed specifically for QKD in 1992 and has become the de-facto standard for all QKD implementations. However, the protocol is highly interactive. Thus, other protocols based on linear block codes such as Hamming codes, low-density parity-check (LDPC) codes, and polar codes have been researched. In particular, reconciliation using LDPC codes has been mainly studied because of its outstanding performance. Nevertheless, with small block size, the bit error rate performance of polar codes under successive-cancellation list (SCL) decoding with a cyclic redundancy check (CRC) is comparable to state-of-the-art turbo and LDPC codes. In this study, we demonstrate the use of polar codes to improve the performance of information reconciliation in a QKD system with small block size. The best decoder for polar codes, a CRC-aided SCL decoder, requires CRC-precoded messages. However, messages that are sifted keys in QKD are obtained arbitrarily as a result of a characteristic of the QKD protocol and cannot be CRC-precoded. We propose a method that allows arbitrarily obtained sifted keys to be CRC precoded by introducing a virtual string. Thus the best decoder can be used for reconciliation using polar codes and improves the efficiency of the protocol.

arXiv:1805.05046•Quantum Information and Computation•Aug 1, 2018•4 citations

Efficient FPGA-Based Implementation of Quantum Key Distribution Post-Processing System

Lianye Liao, Shi‐Hai Sun

Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.

IEEE International Conference on Electronics, Communications and Intelligent Science (ECIS)•May 23, 2025•0 citations

Polar-code-based information reconciliation scheme with the frozen-bit erasure strategy for quantum key distribution

Bang-Ying Tang, Chunqing Wu, Wei Peng +2 more

Information reconciliation (IR) ensures the correctness of quantum key distribution systems by correcting the error bits that existed in the sifted keys. In this article, we propose a polar-code-based IR scheme with the frozen-bit erasure strategy, where an equivalent transmission of sifted keys is conducted so that each frozen bit in the decoding procedure is erased to zero. Thus, our IR scheme is no longer limited by the assumption of true random numbers and can be implemented simply and efficiently. Furthermore, we implement the proposed IR scheme with the fast simplified successive-cancellation list decoder and its throughput reaches $0.68\phantom{\rule{0.16em}{0ex}}\mathrm{Mbps}$ with the yield of 0.8333; when the decoder list size is 16, the block size is $1\phantom{\rule{0.16em}{0ex}}\mathrm{Mb}$ and the quantum bit error rate is 0.02.

arXiv:2203.02074•Physical Review A•Jan 19, 2023•11 citations

Appending Information Reconciliation for Quantum Key Distribution

Han Zhou, Bang-Ying Tang, Si-Chen Li +4 more

Information reconciliation (IR), which corrects the errors in the sifted keys, directly determines the secure key rate and the link distance of quantum key distribution (QKD) systems. In this paper, we propose an appending information reconciliation (AIR) scheme based on polar codes, which achieves high efficiency and ultralow failure probability simultaneously, by gradually disclosing the bit values of the polarized channels with high error probability. The experimental results show that the efficiency of the proposed AIR scheme is closer to the Shannon limit, compared with the state-of-the-art implemented polar-code-based IR schemes, with the overall failure probability around ${10}^{\ensuremath{-}8}$, especially when performed with smaller block sizes. Moreover, the efficiency of the proposed AIR scheme is 1.046, when the block size is 1 Gb and the quantum bit error rate of 0.02. Therefore, the proposed AIR scheme can further eradicate the performance gap between theory and implementation for QKD systems.

arXiv:2204.06971•Physical Review Applied•Oct 10, 2022•12 citations
Abstract Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfections of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has several potential advantages, such as capacity to reach Shannon-limit, high IR efficiency, and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special-purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block-checked successive cancellation list (SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource utilization. Furthermore, the hardware implementation is completed based on Xilinx Zynq UltraScale+ XCZU5EV MPSoC platform and achieves an IR throughput of 15 Mbps with a block length of 212, while less than 20 % of the amount of on-chip resources are used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD.
Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.
Abstract Information reconciliation (IR) corrects the errors in sifted keys and ensures the correctness of quantum key distribution (QKD) systems. Polar codes-based IR schemes can achieve high reconciliation efficiency; however, the incidental high frame error rate decreases the secure key rate of QKD systems. In this article, we propose a Shannon-limit approached (SLA) IR scheme, which mainly contains two phases: the forward reconciliation phase and the acknowledgment reconciliation phase. In the forward reconciliation phase, the sifted key is divided into sub-blocks and performed with the improved block checked successive cancellation list decoder of polar codes. Afterward, only the failure corrected sub-blocks perform the additional acknowledgment reconciliation phase, which decreases the frame error rate of the SLA IR scheme. The experimental results show that the overall failure probability of SLA IR scheme is decreased to 10−810^{-8}10−8 10 - 8 and the efficiency is improved to 1.091 with the IR block length of 128 Mb. Furthermore, the efficiency of the proposed SLA IR scheme is 1.055, approached to Shannon limit, when the quantum bit error rate is 0.02 and the input scale of 1 Gb, which is hundred times larger than the state-of-the-art implemented polar codes-based IR schemes.
Quantum key distribution (QKD) is a cryptographic system that generates an information-theoretically secure key shared by two legitimate parties. QKD consists of two parts: quantum and classical. The latter is referred to as classical post-processing (CPP). Information reconciliation is a part of CPP in which parties are given correlated variables and attempt to eliminate the discrepancies between them while disclosing a minimum amount of information. The elegant reconciliation protocol known as \emph{Cascade} was developed specifically for QKD in 1992 and has become the de-facto standard for all QKD implementations. However, the protocol is highly interactive. Thus, other protocols based on linear block codes such as Hamming codes, low-density parity-check (LDPC) codes, and polar codes have been researched. In particular, reconciliation using LDPC codes has been mainly studied because of its outstanding performance. Nevertheless, with small block size, the bit error rate performance of polar codes under successive-cancellation list (SCL) decoding with a cyclic redundancy check (CRC) is comparable to state-of-the-art turbo and LDPC codes. In this study, we demonstrate the use of polar codes to improve the performance of information reconciliation in a QKD system with small block size. The best decoder for polar codes, a CRC-aided SCL decoder, requires CRC-precoded messages. However, messages that are sifted keys in QKD are obtained arbitrarily as a result of a characteristic of the QKD protocol and cannot be CRC-precoded. We propose a method that allows arbitrarily obtained sifted keys to be CRC precoded by introducing a virtual string. Thus the best decoder can be used for reconciliation using polar codes and improves the efficiency of the protocol.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
Information reconciliation (IR) ensures the correctness of quantum key distribution systems by correcting the error bits that existed in the sifted keys. In this article, we propose a polar-code-based IR scheme with the frozen-bit erasure strategy, where an equivalent transmission of sifted keys is conducted so that each frozen bit in the decoding procedure is erased to zero. Thus, our IR scheme is no longer limited by the assumption of true random numbers and can be implemented simply and efficiently. Furthermore, we implement the proposed IR scheme with the fast simplified successive-cancellation list decoder and its throughput reaches 0.68Mbps0.68\phantom{\rule{0.16em}{0ex}}\mathrm{Mbps}0.68Mbps with the yield of 0.8333; when the decoder list size is 16, the block size is 1Mb1\phantom{\rule{0.16em}{0ex}}\mathrm{Mb}1Mb and the quantum bit error rate is 0.02.
Information reconciliation (IR), which corrects the errors in the sifted keys, directly determines the secure key rate and the link distance of quantum key distribution (QKD) systems. In this paper, we propose an appending information reconciliation (AIR) scheme based on polar codes, which achieves high efficiency and ultralow failure probability simultaneously, by gradually disclosing the bit values of the polarized channels with high error probability. The experimental results show that the efficiency of the proposed AIR scheme is closer to the Shannon limit, compared with the state-of-the-art implemented polar-code-based IR schemes, with the overall failure probability around ${10}^{\ensuremath{-}8}$, especially when performed with smaller block sizes. Moreover, the efficiency of the proposed AIR scheme is 1.046, when the block size is 1 Gb and the quantum bit error rate of 0.02. Therefore, the proposed AIR scheme can further eradicate the performance gap between theory and implementation for QKD systems.