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Opto-Electronics and Communications Conference (OECC)

FPGA-based acceleration of QC-LDPC syndrome encoding for QKD systems

Marco Origlia, Maximilien Pinaud, Luca Maggiani, P. Castoldi, Nicola Andriolli

Published Jun 30, 2024• 0 citations
Publisher

Abstract

Quantum Key Distribution (QKD) systems will be fundamental in ensuring secure communications in future networks. However, due to device imperfections and the random nature of quantum physics itself, these systems need an information reconciliation phase to correct for errors in the key exchange. In particular, for Continuous Variable QKD (CV-QKD) systems, it is possible to employ Multi-Dimensional Reconciliation (MDR) with Quasi-Cyclic LDPC (QC-LDPC) error correction codes. To achieve good reconciliation with low SNR or to limit finite- size effects, large input block codes should be employed. FPGA acceleration is here envisioned. In this work we implemented the encoding for syndromes as large as 1Mbit with a QC-LDPC lift factor of 512 bits and achieve a throughput exceeding 3.55 Gb/s.

DOI
10.1109/oecc54135.2024.10975689

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Quantum Key Distribution (QKD) systems will be fundamental in ensuring secure communications in future networks. However, due to device imperfections and the random nature of quantum physics itself, these systems need an information reconciliation phase to correct for errors in the key exchange. In particular, for Continuous Variable QKD (CV-QKD) systems, it is possible to employ Multi-Dimensional Reconciliation (MDR) with Quasi-Cyclic LDPC (QC-LDPC) error correction codes. To achieve good reconciliation with low SNR or to limit finite- size effects, large input block codes should be employed. FPGA acceleration is here envisioned. In this work we implemented the encoding for syndromes as large as 1Mbit with a QC-LDPC lift factor of 512 bits and achieve a throughput exceeding 3.55 Gb/s.
Information reconciliation (IR) is an integral part of classical data post-processing in quantum key distribution (QKD) and often constitutes a performance bottleneck. Due to the low signal-to-noise ratio, continuous-variable QKD systems require a IR scheme, such as multi-dimensional reconciliation (MDR), which is particularly computationally intensive.In this work we present the hardware architecture of an MDR encoder employing Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. We estimate the required number of flip-flops and the latency of its FPGA implementation. Finally, we investigate the computational bottlenecks and identify solutions to improve the scalability of the proposed implementation.
The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
Abstract The speed at which two remote parties can exchange secret keys in continuous-variable quantum key distribution (CV-QKD) is currently limited by the computational complexity of key reconciliation. Multi-dimensional reconciliation using multi-edge low-density parity-check (LDPC) codes with low code rates and long block lengths has been shown to improve error-correction performance and extend the maximum reconciliation distance. We introduce a quasi-cyclic code construction for multi-edge codes that is highly suitable for hardware-accelerated decoding on a graphics processing unit (GPU). When combined with an 8-dimensional reconciliation scheme, our LDPC decoder achieves an information throughput of 7.16 Kbit/s on a single NVIDIA GeForce GTX 1080 GPU, at a maximum distance of 142 km with a secret key rate of 6.64 × 10−8 bits/pulse for a rate 0.02 code with block length of 106 bits. The LDPC codes presented in this work can be used to extend the previous maximum CV-QKD distance of 100 km to 142 km, while delivering up to 3.50× higher information throughput over the tight upper bound on secret key rate for a lossy channel.
In continuous variable quantum key distribution (CV-QKD) systems, low-density parity check (LDPC) decoders have gained widespread adoption due to their robust error correction capabilities and good adaptability to parallel processing hardware designs. We introduce a syndrome-based normalized min-sum algorithm (S-NMSA) and implement the decoder on FPGAs for high throughput and minimal resource consumption. The decoder utilizes a semi-parallel architecture. The proposed rapid cyclic shifter (RCS) can complete the shift of any dimension matrix in one clock cycle and realizes a significant reduction in hardware resource consumption. The semi-parallel decoding structure attains a 68.5 Mbps processing throughput on the condition that the system clock of the quasi-cyclic (QC) LDPC decoder is 250 Mhz.
Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.
This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.