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International Conference on Transparent Optical Networks

Multi-dimensional reconciliation encoder with quasi-cyclic LDPC codes on FPGA

Marco Origlia, Nicola Andriolli, Luca Maggiani, P. Castoldi, Marco Secondini, Enrico Forestieri, Tobias Rydberg, Tobias Gehring

Published Jul 2, 2023• 0 citations
Publisher

Abstract

Information reconciliation (IR) is an integral part of classical data post-processing in quantum key distribution (QKD) and often constitutes a performance bottleneck. Due to the low signal-to-noise ratio, continuous-variable QKD systems require a IR scheme, such as multi-dimensional reconciliation (MDR), which is particularly computationally intensive.In this work we present the hardware architecture of an MDR encoder employing Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. We estimate the required number of flip-flops and the latency of its FPGA implementation. Finally, we investigate the computational bottlenecks and identify solutions to improve the scalability of the proposed implementation.

DOI
10.1109/icton59386.2023.10207471

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Information reconciliation (IR) is an integral part of classical data post-processing in quantum key distribution (QKD) and often constitutes a performance bottleneck. Due to the low signal-to-noise ratio, continuous-variable QKD systems require a IR scheme, such as multi-dimensional reconciliation (MDR), which is particularly computationally intensive.In this work we present the hardware architecture of an MDR encoder employing Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. We estimate the required number of flip-flops and the latency of its FPGA implementation. Finally, we investigate the computational bottlenecks and identify solutions to improve the scalability of the proposed implementation.
Quantum Key Distribution (QKD) systems will be fundamental in ensuring secure communications in future networks. However, due to device imperfections and the random nature of quantum physics itself, these systems need an information reconciliation phase to correct for errors in the key exchange. In particular, for Continuous Variable QKD (CV-QKD) systems, it is possible to employ Multi-Dimensional Reconciliation (MDR) with Quasi-Cyclic LDPC (QC-LDPC) error correction codes. To achieve good reconciliation with low SNR or to limit finite- size effects, large input block codes should be employed. FPGA acceleration is here envisioned. In this work we implemented the encoding for syndromes as large as 1Mbit with a QC-LDPC lift factor of 512 bits and achieve a throughput exceeding 3.55 Gb/s.
Abstract The speed at which two remote parties can exchange secret keys in continuous-variable quantum key distribution (CV-QKD) is currently limited by the computational complexity of key reconciliation. Multi-dimensional reconciliation using multi-edge low-density parity-check (LDPC) codes with low code rates and long block lengths has been shown to improve error-correction performance and extend the maximum reconciliation distance. We introduce a quasi-cyclic code construction for multi-edge codes that is highly suitable for hardware-accelerated decoding on a graphics processing unit (GPU). When combined with an 8-dimensional reconciliation scheme, our LDPC decoder achieves an information throughput of 7.16 Kbit/s on a single NVIDIA GeForce GTX 1080 GPU, at a maximum distance of 142 km with a secret key rate of 6.64 × 10−8 bits/pulse for a rate 0.02 code with block length of 106 bits. The LDPC codes presented in this work can be used to extend the previous maximum CV-QKD distance of 100 km to 142 km, while delivering up to 3.50× higher information throughput over the tight upper bound on secret key rate for a lossy channel.
This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
Continuous-Variable Quantum Key Distribution (CV-QKD) represents a promising technology for secure communication, but its practical implementation heavily relies on highly efficient information reconciliation (IR) to extract a secret key from correlated quantum data shared over noisy channels. Low-density parity-check codes (LDPC) have emerged as the state-of-the-art solution for this task due to their capacity-approaching performance. However, designing LDPC codes that perform reliably in the very low signal-to-noise ratio (SNR) regime of CV-QKD, while preserving practical implementation complexity, remains a major challenge. This work presents a comprehensive survey of LDPC code design methodologies for CV-QKD, with particular emphasis on three key structural classes: Quasi-Cyclic (QC-LDPC), Multi-Edge Type (MET-LDPC), and their hybrid form (QC-MET-LDPC).
For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.