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arXiv:2211.17019

Real time QKD Post Processing based on Reconfigurable Hardware Acceleration

Foram P. Shingala, Natarajan Venkatachalam, C Selvagangai, Hema Priya S, Dillibabu Shanmugam, Pooja Chandravanshi, Ravindra Pratap Singh

Published Nov 30, 2022• 1 citation
arXivHTMLPDF

Abstract

Key Distillation is an essential component of every Quantum Key Distribution system because it compensates the inherent transmission errors of quantum channel. However, throughput and interoperability aspects of post-processing engine design often neglected, and exiting solutions are not providing any guarantee. In this paper, we propose multiple protocol support high throughput key distillation framework implemented in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). The proposed design uses a Hadoop framework with a map-reduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offer dynamic error correction, a side-channel resistant authentication scheme, and an inbuilt high-speed encryption application, which uses the key for secure communication. We develop a semi automated High level synthesis framework capable of handling different QKD protocols with promising speedup. Overall, the experimental results shows that there is a significant improvement in performance and compatible with any discrete variable QKD systems.

DOI
10.48550/arxiv.2211.17019

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Key Distillation is an essential component of every Quantum Key Distribution system because it compensates the inherent transmission errors of quantum channel. However, throughput and interoperability aspects of post-processing engine design often neglected, and exiting solutions are not providing any guarantee. In this paper, we propose multiple protocol support high throughput key distillation framework implemented in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). The proposed design uses a Hadoop framework with a map-reduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offer dynamic error correction, a side-channel resistant authentication scheme, and an inbuilt high-speed encryption application, which uses the key for secure communication. We develop a semi automated High level synthesis framework capable of handling different QKD protocols with promising speedup. Overall, the experimental results shows that there is a significant improvement in performance and compatible with any discrete variable QKD systems.
Key Distillation is an essential component of every quantum key distribution (QKD) system because it compensates for the inherent transmission errors of a quantum channel. However, the interoperability and throughput aspects of the post-processing components are often neglected. In this paper, we propose a high-throughput key distillation framework that supports multiple QKD protocols, implemented in a field-programmable gate array (FPGA). The proposed design adapts a MapReduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offers dynamic error correction, mutual authentication with a physically unclonable function, and an inbuilt high-speed encryption application that utilizes the key for secure communication. Additionally, we have developed a semi-automated high-level synthesis (HLS) framework that is compatible with any discrete variable QKD system, showing promising speedup. Overall, the experimental results demonstrate a noteworthy enhancement in scalability achieved through the utilization of a single FPGA platform.
Quantum key distribution (QKD), based on quantum mechanics, enables unconditionally secure key exchange even against adversaries with unlimited computing power. As the core of QKD post-processing, information reconciliation (IR) and privacy amplification (PA) ensure key consistency and security by correcting errors and removing leaked information. With the trend toward miniaturized and chip-based QKD systems, post-processing modules require highly integrated designs. FPGAs offer an ideal solution due to their low cost, power efficiency, and flexibility. This paper presents an FPGA-based QKD post-processing architecture using a polar codes-based appending IR algorithm, achieving reconciliation efficiency better than 1.1 under Eµ≥ 0.06 and Rm= 4. A convolution-structured Toeplitz hash module is developed for PA, supporting 53.13 Mbps data rate and 26.45 Mbps key rate with RPA= 0.5. The complete system is implemented on a Xilinx XCKU040 FPGA. Experimental results show support for 176.58 Mbps input, 36.59 Mbps real-time processing, and 17.56 Mbps key output, demonstrating strong performance and engineering suitability. The design features high integration and portability, offering a practical hardware solution for efficient QKD post-processing.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper, we introduce a practical method for expeditious error reconciliation implemented in a field programmable gate array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.
Abstract This paper presents a new hardware implementation of the quantum key distributed cryptography protocol using Field Programmable Gate Array (FPGA). In many security applications, the software implementations of key distribution algorithms are slow and inefficient. In order to solve this problems, new hardware architecture was proposed to speed up the performance and flexibility of key distribution algorithms. The concurrent computing designs quantum key distribution protocol with reducing the hardware area, producing a high throughput and low latency. It also showed high speed processing and consumed low power. An efficient hardware architectural model for quantum key distribution protocol was developed using very high-speed integrated circuit hardware description language (VHDL). This hardware designed to be used with any quantum key distribution protocol to distribution the secret key securely. The hardware implemented and test with Spartan-3 FPGA board and the results show a throughput of 8 Mbps and efficiency of 1.6 Mbps/slice.
The proposed research examines the dynamic partial reconfiguration of FPGA (Field-Programmable Gate Array)-based Coherent One Way (COW) protocol and Differential Phase Shift (DPS) protocol key distillation systems. The purpose of the study is to examine the possible advantages of dynamic partial reconfiguration in cryptographic applications, as well as how it affects resource usage and system adaptability. In terms of security and performance, the proposed COW and DPS key distillation systems show positive outcome. They successfully satisfy the needs for secure key exchange and encryption while striking a balance between computational complexity and resource use. Further, the use of dynamic partial reconfiguration improves the overall effectiveness of the cryptographic system by utilizing resources 29.18% lesser than conventional static FPGA designs.