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International Conference on Control, Communication and Computing (ICCC)

Dynamic Partial Reconfiguration for adaptive QKD key distillation process on FPGA

Saptarsi Halder, Manjith Baby Chellam

Published May 23, 2025• 0 citations
Publisher

Abstract

The proposed research examines the dynamic partial reconfiguration of FPGA (Field-Programmable Gate Array)-based Coherent One Way (COW) protocol and Differential Phase Shift (DPS) protocol key distillation systems. The purpose of the study is to examine the possible advantages of dynamic partial reconfiguration in cryptographic applications, as well as how it affects resource usage and system adaptability. In terms of security and performance, the proposed COW and DPS key distillation systems show positive outcome. They successfully satisfy the needs for secure key exchange and encryption while striking a balance between computational complexity and resource use. Further, the use of dynamic partial reconfiguration improves the overall effectiveness of the cryptographic system by utilizing resources 29.18% lesser than conventional static FPGA designs.

DOI
10.1109/iccc64910.2025.11077253

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The proposed research examines the dynamic partial reconfiguration of FPGA (Field-Programmable Gate Array)-based Coherent One Way (COW) protocol and Differential Phase Shift (DPS) protocol key distillation systems. The purpose of the study is to examine the possible advantages of dynamic partial reconfiguration in cryptographic applications, as well as how it affects resource usage and system adaptability. In terms of security and performance, the proposed COW and DPS key distillation systems show positive outcome. They successfully satisfy the needs for secure key exchange and encryption while striking a balance between computational complexity and resource use. Further, the use of dynamic partial reconfiguration improves the overall effectiveness of the cryptographic system by utilizing resources 29.18% lesser than conventional static FPGA designs.
Key Distillation is an essential component of every quantum key distribution (QKD) system because it compensates for the inherent transmission errors of a quantum channel. However, the interoperability and throughput aspects of the post-processing components are often neglected. In this paper, we propose a high-throughput key distillation framework that supports multiple QKD protocols, implemented in a field-programmable gate array (FPGA). The proposed design adapts a MapReduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offers dynamic error correction, mutual authentication with a physically unclonable function, and an inbuilt high-speed encryption application that utilizes the key for secure communication. Additionally, we have developed a semi-automated high-level synthesis (HLS) framework that is compatible with any discrete variable QKD system, showing promising speedup. Overall, the experimental results demonstrate a noteworthy enhancement in scalability achieved through the utilization of a single FPGA platform.
Key Distillation is an essential component of every Quantum Key Distribution system because it compensates the inherent transmission errors of quantum channel. However, throughput and interoperability aspects of post-processing engine design often neglected, and exiting solutions are not providing any guarantee. In this paper, we propose multiple protocol support high throughput key distillation framework implemented in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). The proposed design uses a Hadoop framework with a map-reduce programming model to efficiently process large chunks of raw data across the limited computing resources of an FPGA. We present a novel hardware-efficient integrated post-processing architecture that offer dynamic error correction, a side-channel resistant authentication scheme, and an inbuilt high-speed encryption application, which uses the key for secure communication. We develop a semi automated High level synthesis framework capable of handling different QKD protocols with promising speedup. Overall, the experimental results shows that there is a significant improvement in performance and compatible with any discrete variable QKD systems.
Quantum key distribution (QKD) provides a secure and effective way of exchanging cryptographic symmetric keys without the possibility of an eavesdropper being undetected. The transmission and detection of the quantum states at the physical layer is the first step to defining a common source of entropy, where both parties will extract a raw key. Over the last few years, continuous variable quantum key distribution (CV-QKD) protocols have become an attractive technology for QKD, providing a low-cost solution that can be easily integrated with the current optical network devices and infrastructure. Unlike other QKD technologies, a CV protocol requires complex and highly computationally demanding digital signal processing (DSP) operations. In that sense, parallel computation tools such as field programmable gate arrays (FPGAs) represent a key element for the practical implementation of this quantum technology and to scale its performance in terms of distance and secret key rate indicators. This work presents an FPGA-based implementation of the physical layer of a CV-QKD transmitter. The proposed architecture and employed protocols are described, and hardware implementation aspects are discussed, including resource occupation analysis, configuration parameters, and timing issues.
Our work aims to introduce an FPGA-based electronics architecture designed to enhance the security of quantum key distribution (QKD) networks. The core focus is on integrating a true random number generator (TRNG) IP in an FPGA-based QKD control electronics implemented on Xilinx’s ZYNQ UltraScale+ based FPGA boards. The work presents the challenges in integrating an existing TRNG IP with QKD FPGA design, different bit and timing requirements, the subsequent speed mismatch issues, support for multiple QKD protocols (Coherent One-Way (CoW) and Differential Phase Shift (DPS)) and user-defined QKD implementations. The integrated design also supports external QRNG/TRNG over USB/Ethernet.
In this paper, a dynamical and adaptive LDPC coding scheme is proposed in order to improve the performance of the cryptographic key distillation protocol of an FSO/CV-QKD system considering the atmospheric turbulence levels that may be present in the classic channel. In this scheme, the Generator and Parity-check matrices of the encoder are modified according to the Rytov variance values estimated in the classical channel in order to improve the final secret key rate of the QKD system. The simulation results show that the final secret key was incremented 87.5 Kbps (from 52.5 Kbps to 140 Kbps) using the adaptive code rate; meaning that the information encrypted and transmitted is increased. In addition, the use of the dynamical encoder avoids the drastically reduction of the final secret key rate when the conditions of the classical channel are considered. Our proposal might be implemented based on the use of high-speed FPGA's and DSP's commercially available.
The increasing efforts by different organizations and countries regarding quantum key distribution (QKD) for secure communications are likely to result in diverse implementations for distinct users. To address this, the development of a software framework for a multi-encoding QKD system is proposed. Part of this framework are the time synchronization between transmitter and receiver, input generation for the arbitrary waveform generator (AWG) used in the implementation, as well as computing the quantum bit error rate (QBER) and secret key rate (SKR) for the employed protocol. This framework support various protocols, such as decoy-state BB84, differential phase-shift (DPS) or coherent one-way (COW), enabling a transmitter to securely exchange keys with different types of receivers. Our approach involves designing a modular and scalable architecture accommodating multiple QKD protocols to ensure compatibility and flexibility. The framework is a step towards interoperability and future-proofing in case current protocols become obsolete.