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IEEE Microwave and Wireless Technology Letters

A Demonstration of Multifloating Superconducting Qubits on a 3-D Flip-Chip Platform With TLS Loss Mitigation via Apertures

Zhen Luo, Thomas Mayer, Daniela Zahn, Carla Morán Guizán, Johannes Weber, Simon Lang, Hannes Bender, L. Schwarzenbach, L. Nebrich, Rui N. Pereira, Amelie Hagelauer

Published Apr 23, 2025• 2 citations
Publisher

Abstract

Flip-chip platforms are among the most promising approaches for scaling up superconducting qubits in quantum computing. This work presents the design, modeling, and analysis of floating transmon qubits implemented on a 3-D flip-chip platform. A major focus during qubit design is addressing coherence challenges caused by two-level system (TLS) losses, particularly from surface interfaces. TLS losses at the metal-air (MA) interface are mitigated by introducing apertures beneath the qubit pads. The aperture size is optimized to balance two key factors: minimizing total TLS loss and ensuring sufficient coupling strength between the transmon and resonator. Subsequently, a packaged 3-D chip comprising 24 floating transmons is demonstrated. The transmission spectrum is measured, with all readout resonators successfully located at their designated positions on the spectrum. Two-tone spectroscopy is demonstrated, enabling precise measurement of the qubit frequency.

DOI
10.1109/lmwt.2025.3559221

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Flip-chip platforms are among the most promising approaches for scaling up superconducting qubits in quantum computing. This work presents the design, modeling, and analysis of floating transmon qubits implemented on a 3-D flip-chip platform. A major focus during qubit design is addressing coherence challenges caused by two-level system (TLS) losses, particularly from surface interfaces. TLS losses at the metal-air (MA) interface are mitigated by introducing apertures beneath the qubit pads. The aperture size is optimized to balance two key factors: minimizing total TLS loss and ensuring sufficient coupling strength between the transmon and resonator. Subsequently, a packaged 3-D chip comprising 24 floating transmons is demonstrated. The transmission spectrum is measured, with all readout resonators successfully located at their designated positions on the spectrum. Two-tone spectroscopy is demonstrated, enabling precise measurement of the qubit frequency.
We present design results of scalable superconducting quantum circuits using the flip-chip assembly. In order to achieve the longest relaxation time (T1T_{1}T1​) of a qubit possible, gap between two chips in flip-chip assembly is determined to be 12 μm where low surface dielectric loss from two-level system (TLS) defects can be achieved while maintaining large readout coupling strength between two chips in the flip-chip assembly. Superconducting transmon qubit design is then optimized to have a target anharmonicity of 200 MHz and to have the longerT1T_{1}T1​in consideration of surface energy participation ratios of TLS defects within the compact footprint. To achieve strong coupling strength but low qubit to qubit crosstalk (ZZ) for fast and high fidelity multi-qubit gates, direct coupler and compact multi-path coupler designs for coupling qubits are compared by numerically solving Hamiltonian of the coupled two qubits. Monte-Carlo simulation results on the yield rate of the extended circuits indicate that low manufacturing errors are required.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of on-chip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS' resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit's Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.
Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.
Fast and high-fidelity qubit readout requires strong coupling between the readout resonator and the feedline. However, such coupling unavoidably enhances qubit decay through the Purcell effect. We present a four-pole broadband Purcell filter implemented on a 3D flip-chip platform to overcome this trade-off. The filter provides a flat 1 GHz passband centered at 7.68 GHz and achieves more than 45 dB suppression at typical qubit frequencies. We demonstrate the filter's compatibility with multiplexed readout using a test chip that integrates six floating readout resonators strongly coupled within the passband. The chip is fabricated using a 150 nm Niobium (Nb) thin-film process and characterized at 20 mK in a cryogenic measurement setup. We also develop an analytical model that accurately captures the filter response and determines the resonance frequencies and external quality factors of the floating resonators directly from their physical geometry, enabling rapid circuit synthesis and design optimization. The proposed design is compact and fabrication-tolerant, making it a practical solution for large-scale superconducting quantum processors.
Abstract The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of on-chip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS’ resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit’s Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.