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arXiv:2008.07652 · Physical Review Applied

Merged-Element Transmon

R. Zhao, S. Park, T. Zhao, Mustafa Bal, C.R.H. McRae, J. Long, D.P. Pappas

Published Dec 1, 2020• 64 citations
arXivHTMLPDF

Abstract

Transmon qubits are ubiquitous in the pursuit of quantum computing using superconducting circuits. However, they have some drawbacks that still need to be addressed. Most importantly, the scalability of transmons is limited by the large device footprint needed to reduce the participation of the lossy capacitive parts of the circuit. In this work, we investigate and evaluate losses in an alternative device geometry, namely, the merged-element transmon (mergemon). To this end, we replace the large external shunt capacitor of a traditional transmon with the intrinsic capacitance of a Josephson junction and achieve an approximately 100 times reduction in qubit dimensions. We report the implementation of the mergemon using a sputtered $\mathrm{Nb}$--amorphous-$\mathrm{Si}$--$\mathrm{Nb}$ trilayer film. In an experiment below 10 mK, the frequency of the readout resonator, capacitively coupled to the mergemon, exhibits a qubit-state-dependent shift in the low-power regime. The device also demonstrates the single-photon and multiphoton transitions that represent a weakly anharmonic system in two-tone spectroscopy. The transition spectra are explained well with master-equation simulations. A participation-ratio analysis identifies the dielectric loss of the amorphous-$\mathrm{Si}$ tunnel barrier and its interfaces as the dominant source for qubit relaxation. We expect the mergemon to achieve high coherence for relatively small device dimensions when implemented with a low-loss, epitaxially grown, and lattice-matched trilayer.

DOI
10.1103/physrevapplied.14.064006

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Transmon qubits are ubiquitous in the pursuit of quantum computing using superconducting circuits. However, they have some drawbacks that still need to be addressed. Most importantly, the scalability of transmons is limited by the large device footprint needed to reduce the participation of the lossy capacitive parts of the circuit. In this work, we investigate and evaluate losses in an alternative device geometry, namely, the merged-element transmon (mergemon). To this end, we replace the large external shunt capacitor of a traditional transmon with the intrinsic capacitance of a Josephson junction and achieve an approximately 100 times reduction in qubit dimensions. We report the implementation of the mergemon using a sputtered Nb\mathrm{Nb}Nb--amorphous-Si\mathrm{Si}Si--Nb\mathrm{Nb}Nb trilayer film. In an experiment below 10 mK, the frequency of the readout resonator, capacitively coupled to the mergemon, exhibits a qubit-state-dependent shift in the low-power regime. The device also demonstrates the single-photon and multiphoton transitions that represent a weakly anharmonic system in two-tone spectroscopy. The transition spectra are explained well with master-equation simulations. A participation-ratio analysis identifies the dielectric loss of the amorphous-Si\mathrm{Si}Si tunnel barrier and its interfaces as the dominant source for qubit relaxation. We expect the mergemon to achieve high coherence for relatively small device dimensions when implemented with a low-loss, epitaxially grown, and lattice-matched trilayer.
We demonstrate a superconducting transmon qubit in which a Josephson junction has been engineered to act as its own parallel shunt capacitor. This merged-element transmon potentially offers a smaller footprint than conventional transmons. Because it concentrates the electromagnetic energy inside the junction, it reduces the relative electric field participation from other interfaces. By combining micrometer-scale Al\mathrm{Al}Al/AlO\mathrm{Al}\mathrm{O}AlOx{}_{x}x​/Al\mathrm{Al}Al junctions with long oxidations, we produce functional devices with EJ/EC{E}_{J}/{E}_{C}EJ​/EC​ in the low-transmon regime (${E}_{J}/{E}_{C}\ensuremath{\lesssim}30$). Cryogenic III-VVV measurements show a sharp dI/dVdI/dVdI/dV structure with low subgap conduction. Qubit spectroscopy of tunable versions shows a small number of avoided level crossings, suggesting the presence of two-level systems. We observe mean T1{T}_{1}T1​ times typically in the range of $10--90\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$, with some annealed devices exhibiting ${T}_{1}>100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ over several hours. The results suggest that energy relaxation in conventional small-junction transmons is not limited by junction loss.
A merged-element transmon (MET) device based on silicon (Si) fins is proposed, and the first steps to form such a “FinMET” are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on parallel sidewall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, potentially lossy AlOx, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer or digital etching; (4) potentially reducing the footprint by several orders of magnitude; and (5) allowing scalable fabrication. Here, as a first step to making such a device, the fabrication of Si fin capacitors on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. These fin capacitors are then fabricated into lumped element resonator circuits and probed using low-temperature microwave measurements. Further thinning of silicon junctions toward the tunneling regime will enable the scalable fabrication of FinMET devices based on existing silicon technology while simultaneously avoiding lossy amorphous dielectrics for the tunnel barriers.
We developed transmon qubits based on epitaxial tunnel junctions and interdigitated capacitors. This multileveled qubit, patterned by use of all-optical lithography, is a step towards scalable qubits with a high integration density. The relaxation time T1 is 0.72−0.86 μs and the ensemble dephasing time T2* is slightly larger than T1. The dephasing time T2 (1.36 μs) is nearly energy-relaxation-limited. Qubit spectroscopy yields weaker level splitting than observed in qubits with amorphous barriers in equivalent-size junctions. The qubit’s inferred microwave loss closely matches the weighted losses of the individual elements (junction, wiring dielectric, and interdigitated capacitor), determined by independent resonator measurements.
State-of-the-art superconducting qubits rely on a limited set of thin-film materials. Expanding their materials palette can improve performance, extend operating regimes, and introduce new functionalities, but conventional thin-film fabrication hinders systematic exploration of new material combinations. Van der Waals (vdW) materials offer a highly modular crystalline platform that facilitates such exploration while enabling gate-tunability, higher-temperature operation, and compact qubit geometries. Yet it remains unknown whether a fully vdW superconducting qubit can support quantum coherence and what mechanisms dominate loss at both low and elevated temperatures in such a device. Here we demonstrate quantum-coherent merged-element transmons made entirely from vdW Josephson junctions. These first-generation, fully crystalline qubits achieve microsecond lifetimes in an ultra-compact footprint without external shunt capacitors. Energy relaxation measurements, together with microwave characterization of vdW capacitors, point to dielectric loss as the dominant relaxation channel up to hundreds of millikelvin. These results establish vdW materials as a viable platform for compact superconducting quantum devices.
A merged-element transmon (MET) device, based on Si fins, is proposed and the steps to form such a are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on the parallel side-wall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, lossy Al2O3, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer digital etching; (4) reducing the footprint by four orders of magnitude; and (5) allowing scalable fabrication. Here, fabrication of Si fins on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. The formation of FinMET devices is expected to allow tunnel junction patterning with optical lithography. This facilitates uniform fabrication on Si wafers based on existing infrastructure for fin-based devices while simultaneously avoiding lossy amorphous dielectrics for tunnel barriers.
State-of-the-art transmon qubits rely on large capacitors, which systematically improve their coherence due to reduced surface-loss participation. However, this approach increases both the footprint and the parasitic cross-coupling and is ultimately limited by radiation losses---a potential roadblock for scaling up quantum processors to millions of qubits. In this work we present transmon qubits with sizes as low as $36\phantom{\rule{0.2em}{0ex}}\ifmmode\times\else\texttimes\fi{}\phantom{\rule{0.2em}{0ex}}39\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{2}$ with $\ensuremath{\gtrsim}100$-nm-wide vacuum-gap capacitors that are micromachined from commercial silicon-on-insulator wafers and shadow evaporated with aluminum. We achieve a vacuum participation ratio up to 99.6% in an in-plane design that is compatible with standard coplanar circuits. Qubit relaxation-time measurements for small gaps with high zero-point electric field variance of up to 22 V/m reveal a double exponential decay indicating comparably strong qubit interaction with long-lived two-level systems. The exceptionally high selectivity of up to 20 dB to the superconductor-vacuum interface allows us to precisely back out the sub-single-photon dielectric loss tangent of aluminum oxide previously exposed to ambient conditions. In terms of future scaling potential, we achieve a ratio of qubit quality factor to a footprint area equal to $20\phantom{\rule{0.2em}{0ex}}\text{\ensuremath{\mu}}{\mathrm{m}}^{\ensuremath{-}2}$, which is comparable with the highest T1{T}_{1}T1​ devices relying on larger geometries, a value that could improve substantially for lower surface-loss superconductors.