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Merged-element transmons on Si fins: the FinMET

Aranya Goswami, Anthony McFadden, Hadass S. Inbar, Ruichen Zhao, Corey Rae McRae, C. J. Palmstrøm, David P. Pappas

Published Aug 25, 2021• 0 citations
OpenAlex

Abstract

A merged-element transmon (MET) device, based on Si fins, is proposed and the steps to form such a are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on the parallel side-wall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, lossy Al2O3, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer digital etching; (4) reducing the footprint by four orders of magnitude; and (5) allowing scalable fabrication. Here, fabrication of Si fins on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. The formation of FinMET devices is expected to allow tunnel junction patterning with optical lithography. This facilitates uniform fabrication on Si wafers based on existing infrastructure for fin-based devices while simultaneously avoiding lossy amorphous dielectrics for tunnel barriers.

Related papers

Towards merged-element transmons using silicon fins: The FinMET

Aranya Goswami, Anthony McFadden, Tongyu Zhao +7 more

A merged-element transmon (MET) device based on silicon (Si) fins is proposed, and the first steps to form such a “FinMET” are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on parallel sidewall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, potentially lossy AlOx, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer or digital etching; (4) potentially reducing the footprint by several orders of magnitude; and (5) allowing scalable fabrication. Here, as a first step to making such a device, the fabrication of Si fin capacitors on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. These fin capacitors are then fabricated into lumped element resonator circuits and probed using low-temperature microwave measurements. Further thinning of silicon junctions toward the tunneling regime will enable the scalable fabrication of FinMET devices based on existing silicon technology while simultaneously avoiding lossy amorphous dielectrics for the tunnel barriers.

arXiv:2108.11519•Applied Physics Letters•Aug 8, 2022•13 citations

Merged-Element Transmon

R. Zhao, S. Park, T. Zhao +4 more

Transmon qubits are ubiquitous in the pursuit of quantum computing using superconducting circuits. However, they have some drawbacks that still need to be addressed. Most importantly, the scalability of transmons is limited by the large device footprint needed to reduce the participation of the lossy capacitive parts of the circuit. In this work, we investigate and evaluate losses in an alternative device geometry, namely, the merged-element transmon (mergemon). To this end, we replace the large external shunt capacitor of a traditional transmon with the intrinsic capacitance of a Josephson junction and achieve an approximately 100 times reduction in qubit dimensions. We report the implementation of the mergemon using a sputtered $\mathrm{Nb}$--amorphous-$\mathrm{Si}$--$\mathrm{Nb}$ trilayer film. In an experiment below 10 mK, the frequency of the readout resonator, capacitively coupled to the mergemon, exhibits a qubit-state-dependent shift in the low-power regime. The device also demonstrates the single-photon and multiphoton transitions that represent a weakly anharmonic system in two-tone spectroscopy. The transition spectra are explained well with master-equation simulations. A participation-ratio analysis identifies the dielectric loss of the amorphous-$\mathrm{Si}$ tunnel barrier and its interfaces as the dominant source for qubit relaxation. We expect the mergemon to achieve high coherence for relatively small device dimensions when implemented with a low-loss, epitaxially grown, and lattice-matched trilayer.

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Fabrication and characterization of low-loss Al/Si/Al parallel plate capacitors for superconducting quantum information applications

Anthony McFadden, Aranya Goswami, Tongyu Zhao +7 more

Abstract Increasing the density of superconducting circuits requires compact components, however, superconductor-based capacitors typically perform worse as dimensions are reduced due to loss at surfaces and interfaces. Here, parallel plate capacitors composed of aluminum-contacted, crystalline silicon fins are shown to be a promising technology for use in superconducting circuits by evaluating the performance of lumped element resonators and transmon qubits. High aspect ratio Si-fin capacitors having widths below 300 nm with an approximate total height of 3 μm are fabricated using anisotropic wet etching of Si(110) substrates followed by aluminum metallization. The single-crystal Si capacitors are incorporated in lumped element resonators and transmons by shunting them with lithographically patterned aluminum inductors and conventional A l/A l O x /A l Josephson junctions respectively. Microwave characterization of these devices suggests state-of-the-art performance for superconducting parallel plate capacitors with low power internal quality factor of lumped element resonators greater than 500 k and qubit T 1 times greater than 25 μs. These results suggest that Si-Fins are a promising technology for applications that require low-loss, compact, superconductor-based capacitors with minimal stray capacitance.

arXiv:2408.01369•npj Quantum Information•Jan 22, 2025•5 citations

Coherence in a transmon qubit with epitaxial tunnel junctions

Martin P. Weides, Jeffrey S. Kline, Michael R. Vissers +5 more

We developed transmon qubits based on epitaxial tunnel junctions and interdigitated capacitors. This multileveled qubit, patterned by use of all-optical lithography, is a step towards scalable qubits with a high integration density. The relaxation time T1 is 0.72−0.86 μs and the ensemble dephasing time T2* is slightly larger than T1. The dephasing time T2 (1.36 μs) is nearly energy-relaxation-limited. Qubit spectroscopy yields weaker level splitting than observed in qubits with amorphous barriers in equivalent-size junctions. The qubit’s inferred microwave loss closely matches the weighted losses of the individual elements (junction, wiring dielectric, and interdigitated capacitor), determined by independent resonator measurements.

arXiv:1111.5083•Applied Physics Letters•Dec 26, 2011•52 citations

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H. Jonathon Mamin, Elbert Huang, Santino D. Carnevale +12 more

We demonstrate a superconducting transmon qubit in which a Josephson junction has been engineered to act as its own parallel shunt capacitor. This merged-element transmon potentially offers a smaller footprint than conventional transmons. Because it concentrates the electromagnetic energy inside the junction, it reduces the relative electric field participation from other interfaces. By combining micrometer-scale $\mathrm{Al}$/$\mathrm{Al}\mathrm{O}$${}_{x}$/$\mathrm{Al}$ junctions with long oxidations, we produce functional devices with ${E}_{J}/{E}_{C}$ in the low-transmon regime (${E}_{J}/{E}_{C}\ensuremath{\lesssim}30$). Cryogenic $I$-$V$ measurements show a sharp $dI/dV$ structure with low subgap conduction. Qubit spectroscopy of tunable versions shows a small number of avoided level crossings, suggesting the presence of two-level systems. We observe mean ${T}_{1}$ times typically in the range of $10--90\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$, with some annealed devices exhibiting ${T}_{1}>100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ over several hours. The results suggest that energy relaxation in conventional small-junction transmons is not limited by junction loss.

arXiv:2103.09163•Physical Review Applied•Aug 13, 2021•57 citations

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

Andrew D. Beyer, Matthew I. Hollister, Jack Sayers +3 more

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

•Sep 21, 2016•0 citations
A merged-element transmon (MET) device, based on Si fins, is proposed and the steps to form such a are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on the parallel side-wall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, lossy Al2O3, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer digital etching; (4) reducing the footprint by four orders of magnitude; and (5) allowing scalable fabrication. Here, fabrication of Si fins on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. The formation of FinMET devices is expected to allow tunnel junction patterning with optical lithography. This facilitates uniform fabrication on Si wafers based on existing infrastructure for fin-based devices while simultaneously avoiding lossy amorphous dielectrics for tunnel barriers.
A merged-element transmon (MET) device based on silicon (Si) fins is proposed, and the first steps to form such a “FinMET” are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on parallel sidewall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, potentially lossy AlOx, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses; (2) minimizing the formation of two-level system spectral features; (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer or digital etching; (4) potentially reducing the footprint by several orders of magnitude; and (5) allowing scalable fabrication. Here, as a first step to making such a device, the fabrication of Si fin capacitors on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. These fin capacitors are then fabricated into lumped element resonator circuits and probed using low-temperature microwave measurements. Further thinning of silicon junctions toward the tunneling regime will enable the scalable fabrication of FinMET devices based on existing silicon technology while simultaneously avoiding lossy amorphous dielectrics for the tunnel barriers.
Transmon qubits are ubiquitous in the pursuit of quantum computing using superconducting circuits. However, they have some drawbacks that still need to be addressed. Most importantly, the scalability of transmons is limited by the large device footprint needed to reduce the participation of the lossy capacitive parts of the circuit. In this work, we investigate and evaluate losses in an alternative device geometry, namely, the merged-element transmon (mergemon). To this end, we replace the large external shunt capacitor of a traditional transmon with the intrinsic capacitance of a Josephson junction and achieve an approximately 100 times reduction in qubit dimensions. We report the implementation of the mergemon using a sputtered Nb\mathrm{Nb}Nb--amorphous-Si\mathrm{Si}Si--Nb\mathrm{Nb}Nb trilayer film. In an experiment below 10 mK, the frequency of the readout resonator, capacitively coupled to the mergemon, exhibits a qubit-state-dependent shift in the low-power regime. The device also demonstrates the single-photon and multiphoton transitions that represent a weakly anharmonic system in two-tone spectroscopy. The transition spectra are explained well with master-equation simulations. A participation-ratio analysis identifies the dielectric loss of the amorphous-Si\mathrm{Si}Si tunnel barrier and its interfaces as the dominant source for qubit relaxation. We expect the mergemon to achieve high coherence for relatively small device dimensions when implemented with a low-loss, epitaxially grown, and lattice-matched trilayer.
Abstract Increasing the density of superconducting circuits requires compact components, however, superconductor-based capacitors typically perform worse as dimensions are reduced due to loss at surfaces and interfaces. Here, parallel plate capacitors composed of aluminum-contacted, crystalline silicon fins are shown to be a promising technology for use in superconducting circuits by evaluating the performance of lumped element resonators and transmon qubits. High aspect ratio Si-fin capacitors having widths below 300 nm with an approximate total height of 3 μm are fabricated using anisotropic wet etching of Si(110) substrates followed by aluminum metallization. The single-crystal Si capacitors are incorporated in lumped element resonators and transmons by shunting them with lithographically patterned aluminum inductors and conventional A l/A l O x /A l Josephson junctions respectively. Microwave characterization of these devices suggests state-of-the-art performance for superconducting parallel plate capacitors with low power internal quality factor of lumped element resonators greater than 500 k and qubit T 1 times greater than 25 μs. These results suggest that Si-Fins are a promising technology for applications that require low-loss, compact, superconductor-based capacitors with minimal stray capacitance.
We developed transmon qubits based on epitaxial tunnel junctions and interdigitated capacitors. This multileveled qubit, patterned by use of all-optical lithography, is a step towards scalable qubits with a high integration density. The relaxation time T1 is 0.72−0.86 μs and the ensemble dephasing time T2* is slightly larger than T1. The dephasing time T2 (1.36 μs) is nearly energy-relaxation-limited. Qubit spectroscopy yields weaker level splitting than observed in qubits with amorphous barriers in equivalent-size junctions. The qubit’s inferred microwave loss closely matches the weighted losses of the individual elements (junction, wiring dielectric, and interdigitated capacitor), determined by independent resonator measurements.
We demonstrate a superconducting transmon qubit in which a Josephson junction has been engineered to act as its own parallel shunt capacitor. This merged-element transmon potentially offers a smaller footprint than conventional transmons. Because it concentrates the electromagnetic energy inside the junction, it reduces the relative electric field participation from other interfaces. By combining micrometer-scale Al\mathrm{Al}Al/AlO\mathrm{Al}\mathrm{O}AlOx{}_{x}x​/Al\mathrm{Al}Al junctions with long oxidations, we produce functional devices with EJ/EC{E}_{J}/{E}_{C}EJ​/EC​ in the low-transmon regime (${E}_{J}/{E}_{C}\ensuremath{\lesssim}30$). Cryogenic III-VVV measurements show a sharp dI/dVdI/dVdI/dV structure with low subgap conduction. Qubit spectroscopy of tunable versions shows a small number of avoided level crossings, suggesting the presence of two-level systems. We observe mean T1{T}_{1}T1​ times typically in the range of $10--90\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$, with some annealed devices exhibiting ${T}_{1}>100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ over several hours. The results suggest that energy relaxation in conventional small-junction transmons is not limited by junction loss.
We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.