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RSFQ circuit with integrated synchronisation cell

Pascal Febvre, Torsten Reich, Hannes Toepfer, J. Kunert, Hans‐Georg Meyer, Thomas Ortlepp, Friedrich Uhlmann

Published Jun 22, 2008• 0 citations
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Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.
Design and Operation of RSFQ Cell Library Fabricated by Using a 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Nb Technology
A 10-kA/cm2Nb/AlOchi/Nb junction technology for rapid single flux quantum (RSFQ) integrated circuits has been developed. Modifying our standard 1.6-kA/cm2cell library, we have implemented elementary cells used to build RSFQ digital-to-analog converters for ac voltage standard applications. The 10-kA/cm2library cells have been fabricated by utilizing existing process tools. Correct operations of the circuits have been confirmed at low speed. The maximum operating frequencies evaluated by an average-voltage measurement technique were consistent with the scaling rules of RSFQ circuits.
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.