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International Conference on Control Systems, Mathematical Modeling, Automation and Energy Efficiency (SUMMA)

Quantum Computing Simulation on VLIW Microprocessors

Nikita Bocharov

Published Nov 13, 2024• 0 citations
Publisher

Abstract

This paper presents the development of a quantum computing simulator on the Elbrus VLIW microprocessor architecture. The simulator is designed to efficiently simulate quantum algorithms by leveraging the parallelism and instruction-level optimization provided by the Elbrus processors. Key features of the simulator include integration with the Elbrus Media Library (EML) to accelerate matrix operations, support for quantum circuit design through a graphical user interface, and the ability to simulate up to 30 qubits using standard storage methods. Additionally, the use of sparse matrix techniques allows for the simulation of larger quantum systems, potentially up to 35 qubits, within a 32 GB memory limit. The results highlight the potential of using VLIW microprocessors for quantum computing simulations and provide insights into the future scalability of such systems.

DOI
10.1109/summa64428.2024.10803673

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This paper presents the development of a quantum computing simulator on the Elbrus VLIW microprocessor architecture. The simulator is designed to efficiently simulate quantum algorithms by leveraging the parallelism and instruction-level optimization provided by the Elbrus processors. Key features of the simulator include integration with the Elbrus Media Library (EML) to accelerate matrix operations, support for quantum circuit design through a graphical user interface, and the ability to simulate up to 30 qubits using standard storage methods. Additionally, the use of sparse matrix techniques allows for the simulation of larger quantum systems, potentially up to 35 qubits, within a 32 GB memory limit. The results highlight the potential of using VLIW microprocessors for quantum computing simulations and provide insights into the future scalability of such systems.
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Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
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Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory-intensive, making hardware emulators an attractive alternative. This article introduces a digital architecture, designed to emulate quantum computing on low-tier Field-Programmable Gate Arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates quantum algorithm verification using a RISC-like structure and efficiently handling sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. The architecture is validated against the Qiskit state vector simulator, successfully emulating sixteen qubits on a Xilinx Kria KV260 SoM.