In this chapter, a pulse-based method to facilitate equilibrium transitions in a superconductor memory cell is developed. In a cryogenic environment, non-dissipative storage of non-binary memory states has the potential to drastically increase energy efficiency per operation and decrease the number of memory cells per unit area. Memory cells in consideration are fabricated with Josephson junctions, which are superconducting devices analogous to the classical bit. Dynamics of a memory cell are identical to an array of coupled nonlinear oscillators, which have no known analytic solution. Despite this difficulty, a novel closed-form control technique is developed to design pulses that force stable state transitions in a memory cell. Simulation results are shown to verify the proposed solution.
In this chapter, a pulse-based method to facilitate equilibrium transitions in a superconductor memory cell is developed. In a cryogenic environment, non-dissipative storage of non-binary memory states has the potential to drastically increase energy efficiency per operation and decrease the number of memory cells per unit area. Memory cells in consideration are fabricated with Josephson junctions, which are superconducting devices analogous to the classical bit. Dynamics of a memory cell are identical to an array of coupled nonlinear oscillators, which have no known analytic solution. Despite this difficulty, a novel closed-form control technique is developed to design pulses that force stable state transitions in a memory cell. Simulation results are shown to verify the proposed solution.
Energy efficient cryogenic memory and Josephson junction arrays have the potential of revolutionizing high-performance computing systems based on single flux quantum logic. In this paper, a pulse control is designed to switch among stable equilibrium states of a Josephson junction array. Josephson junction arrays have the ability to store state information at low temperatures and energies, which naturally is useful for cryogenic memory applications. Although typical memory applications involve binary states, as a memory cell, the Josephson junction array has the ability to occupy nonbinary states given the nonlinear nature of the dynamics, which can lead to a reduced number of cells required in practical applications among other advantages. Transitions between states can be achieved through experimental testing for specific transitions, however, there are no known closed-form solutions to arbitrarily transition from one stable state to another. The system dynamics are similar to an array of coupled nonlinear oscillators, for which there is no known analytical solution. By providing an energy-based analysis for the junction array, a lower bound is determined and system trajectories are closely approximated such that the array is capable of transitioning between any desired stable equilibrium states under a Gaussian pulse input.
Abstract Storage of a single magnetic flux quantum in a superconducting loop containing a Josephson junction represents a promising unit cell configuration for construction of a cryogenic memory of superconducting digital circuits. However, application of a DC bias current is required for operation of such a memory cell to maintain trapping of the flux quantum in the storage loop. In this work, we present a superconducting memory cell that uses a superconducting-magnetic π junction. The cell characteristics show flux quantum hysteresis centering at the zero-bias current. We develop a fabrication process that combines superconductor–ferromagnet–superconductor (SFS) junctions with superconductor–normal metal–superconductor (SNS) junctions. The critical current density of the SFS junctions shows a 0–π oscillation as a function of the ferromagnetic layer thickness. The formation of the π junction is confirmed further by the flux modulation curves of a superconducting quantum interference device made from SNS junctions with an additional SFS junction.
Abstract In this paper we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.
Abstract The ongoing progress of superconducting logic systems with Josephson junctions as base elements requires the development of compatible cryogenic memory. Long enough junctions subject to magnetic field host quantum phase 2 π -singularities—Josephson vortices. Here, we report the realization of the superconducting memory cell whose state is encoded by the number of present Josephson vortices. By integrating the junction into a coplanar resonator and by applying a microwave excitation well below the critical current, we are able to control the state of the system in an energy-efficient and non-destructive manner. The memory effect arises due to the presence of the natural edge barrier for Josephson vortices. The performance of the device is evaluated, and the routes for creating scalable cryogenic memories directly compatible with superconducting microwave technologies are discussed.
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.
Adiabatic superconducting logic circuits can ensure the practical implementation of operations with the energy dissipation below the Landauer limit. However, applications of the existing solutions are limited because of two contradictory requirements of a high energy efficiency and a sufficiently fast response of devices. Josephson junctions with a negative critical current (π junctions) allow one to obtain a certain form of the potential energy of superconducting circuits and, as a result, a practically required degree of control of dynamic processes in the proposed reversible logic cells. The features of the current transport and balance of Josephson phases in circuits with π junctions make it possible to improve the coupling between the parts of a reversible computer by a factor more than 2. At the same time, the continuous evolution of the state is ensured at higher critical currents and higher characteristic voltages of the main Josephson junctions of adiabatic superconducting logic cells, which allows an increase in the response rate.