Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Superconducting Nanowire Integrated Circuits for Scalable Cryogenic Memory

Owen Medeiros

Published May 1, 2025• 0 citations
OpenAlex

Abstract

Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.

Related papers

A scalable superconducting nanowire memory cell and preliminary array test

Brenden Butters, Reza Baghdadi, Murat Onen +3 more

Abstract There has been a demand for a scalable superconducting memory technology for cryogenic computing for some time. This demand has proven difficult to satisfy due to the simultaneous need for high speed operation, low power consumption, and high density, all while maintaining cryogenic and SFQ compatibility. In an effort to satisfy this demand, we have developed a simple memory cell based on our prior work with nanowire-based memories. Due to the memory cell’s reliance on kinetic inductance, the cell can be scaled to almost any size. The cell has been designed specifically such that it can easily form into an array simply by arranging in a 2D pattern. This design eliminated the need for external addressing circuitry. This new cell, when operated in isolation and without the heater, performs very well with predicted bit error rates around 10 −17 . However, preliminary array tests show that while the memory operates, the predicted error rates rise to 1.5 × 10 −3 . We believe that this issue is predominantly due to the hTron-channel kinetic inductance dramatically changing upon the application of the row-select heaters. This issue might be addressed by designing the cell to compensate for the change in kinetic inductance when the heater is activated. If this remedy proves to be effective, then this memory would enable the development of compact and scalable memory arrays.

Superconductor Science and Technology•Dec 7, 2020•20 citations

Scalable Superconducting Nanowire Memory Array with Row-Column Addressing

Owen Medeiros, Matteo Castellani, Valentin Karam +6 more

Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6$\,$Mb/cm$^{2}$. The array operates at $1.3\,$K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a $4\times 4$ array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of $10^{-5}$. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.

arXiv:2503.22897•Mar 28, 2025•1 citation

A compact superconducting nanowire memory element operated by nanowire cryotrons

Qingyuan Zhao, Emily Toomey, Butters, Brendan Andrew +4 more

A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.

•Feb 1, 2018•51 citations

A compact superconducting nanowire memory element operated by nanowire cryotrons

Qingyuan Zhao, Emily Toomey, Brenden Butters +4 more

Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.

arXiv:1711.08290•Superconductor Science and Technology•Jan 16, 2018•54 citations

Monolithic integrated superconducting nanowire digital encoder

Yang‐Hui Huang, Qingyuan Zhao, Hao Hao +11 more

Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.

Applied Physics Letters•May 6, 2024•12 citations

Superconducting Nanowire Single-Photon Detectors (SNSPDs) and Scalable Quantum Photonic Integrated Circuits: Cryogenic Quantum Light Sources, Multiplexed Readout Architectures, and Quantum Key Distribution

Wahengbam Thouba Singh, Vishal Kumar, Dr. Vishal Shrivastava, Dr. Akhil Pandey

Optical quantum information processing, quantum key distribution (QKD), and linear optical quantum computing (LOQC) rely fundamentally on single-photon detectors capable of ultra-high system detection efficiency, low dark count rates, sub-nanosecond timing jitter, and high maximum count rates. Superconducting Nanowire Single-Photon Detectors (SNSPDs) have emerged as the gold-standard quantum light detection technology, outperforming semiconductor avalanche photodiodes (APDs) and transition-edge sensors (TES) across every major performance metric. By biasing ultrathin superconducting nanometric strips (e.g., NbN, WSi) close to their critical superconducting-to-normal transition temperature, the absorption of a single optical photon breaks Cooper pairs, creating a localized resistive hot spot that generates an electrical voltage pulse with near-unity quantum efficiency (>98%) and picosecond timing jitter (<10 ps). Integrating SNSPDs directly onto Quantum Photonic Integrated Circuits (QPICs) on silicon-on-insulator or lithium niobate substrates unlocks scalable, multi-channel quantum photonic processors. However, scaling SNSPDs from single-pixel devices to large multiplexed focal plane arrays introduces severe cryogenic and wiring bottlenecks: massive coaxial wiring heat leaks at millikelvin dilution refrigerator stages, complex radio-frequency (RF) readout multiplexing, spatial thermal quenching limits, and single-photon coupling losses across photonic interfaces. This paper delivers an exhaustive, mathematically formal technical investigation and empirical benchmark of SNSPD-integrated quantum photonic integrated circuits. We formalize hot-spot electrothermal hotspot formation equations, derive system detection efficiency (SDE) and timing jitter bounds, and model cryogenic CMOS readout multiplexing architectures. Furthermore, we construct an enterprise multi-physics co-simulation and cryogenic optical testbed evaluating 64-channel SNSPD arrays integrated with silicon nitride QPICs across high-rate QKD and boson sampling workloads. Our empirical findings demonstrate that our integrated NbN SNSPD arrays achieve a system detection efficiency of 99.4% at 1550 nm, a timing jitter of 6.2 ps, and a dark count rate below 10^-4 Hz while operating at 2.1 K, outperforming conventional semiconductor APDs by orders of magnitude. Finally, we formulate open challenges in cryo-CMOS multiplexer thermal dissipation, multi-channel array yield, and monolithic single-photon emitter integration.

•Oct 25, 2026•0 citations
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.
Abstract There has been a demand for a scalable superconducting memory technology for cryogenic computing for some time. This demand has proven difficult to satisfy due to the simultaneous need for high speed operation, low power consumption, and high density, all while maintaining cryogenic and SFQ compatibility. In an effort to satisfy this demand, we have developed a simple memory cell based on our prior work with nanowire-based memories. Due to the memory cell’s reliance on kinetic inductance, the cell can be scaled to almost any size. The cell has been designed specifically such that it can easily form into an array simply by arranging in a 2D pattern. This design eliminated the need for external addressing circuitry. This new cell, when operated in isolation and without the heater, performs very well with predicted bit error rates around 10 −17 . However, preliminary array tests show that while the memory operates, the predicted error rates rise to 1.5 × 10 −3 . We believe that this issue is predominantly due to the hTron-channel kinetic inductance dramatically changing upon the application of the row-select heaters. This issue might be addressed by designing the cell to compensate for the change in kinetic inductance when the heater is activated. If this remedy proves to be effective, then this memory would enable the development of compact and scalable memory arrays.
Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6 \,Mb/cm2^{2}2. The array operates at 1.3 1.3\,1.3K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a 4×44\times 44×4 array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of 10−510^{-5}10−5. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.
Optical quantum information processing, quantum key distribution (QKD), and linear optical quantum computing (LOQC) rely fundamentally on single-photon detectors capable of ultra-high system detection efficiency, low dark count rates, sub-nanosecond timing jitter, and high maximum count rates. Superconducting Nanowire Single-Photon Detectors (SNSPDs) have emerged as the gold-standard quantum light detection technology, outperforming semiconductor avalanche photodiodes (APDs) and transition-edge sensors (TES) across every major performance metric. By biasing ultrathin superconducting nanometric strips (e.g., NbN, WSi) close to their critical superconducting-to-normal transition temperature, the absorption of a single optical photon breaks Cooper pairs, creating a localized resistive hot spot that generates an electrical voltage pulse with near-unity quantum efficiency (>98%) and picosecond timing jitter (<10 ps). Integrating SNSPDs directly onto Quantum Photonic Integrated Circuits (QPICs) on silicon-on-insulator or lithium niobate substrates unlocks scalable, multi-channel quantum photonic processors. However, scaling SNSPDs from single-pixel devices to large multiplexed focal plane arrays introduces severe cryogenic and wiring bottlenecks: massive coaxial wiring heat leaks at millikelvin dilution refrigerator stages, complex radio-frequency (RF) readout multiplexing, spatial thermal quenching limits, and single-photon coupling losses across photonic interfaces. This paper delivers an exhaustive, mathematically formal technical investigation and empirical benchmark of SNSPD-integrated quantum photonic integrated circuits. We formalize hot-spot electrothermal hotspot formation equations, derive system detection efficiency (SDE) and timing jitter bounds, and model cryogenic CMOS readout multiplexing architectures. Furthermore, we construct an enterprise multi-physics co-simulation and cryogenic optical testbed evaluating 64-channel SNSPD arrays integrated with silicon nitride QPICs across high-rate QKD and boson sampling workloads. Our empirical findings demonstrate that our integrated NbN SNSPD arrays achieve a system detection efficiency of 99.4% at 1550 nm, a timing jitter of 6.2 ps, and a dark count rate below 10^-4 Hz while operating at 2.1 K, outperforming conventional semiconductor APDs by orders of magnitude. Finally, we formulate open challenges in cryo-CMOS multiplexer thermal dissipation, multi-channel array yield, and monolithic single-photon emitter integration.