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Superconductor Science and Technology

Memory cell operation based on small Josephson junctions arrays

Yehuda Y. Braiman, Niketh Nair, Jacob D. Rezac, Neena Imam

Published Oct 14, 2016• 11 citations
Publisher

Abstract

Abstract In this paper we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.

DOI
10.1088/0953-2048/29/12/124003

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Abstract In this paper we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.
Abstract In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.
A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
Energy efficient cryogenic memory and Josephson junction arrays have the potential of revolutionizing high-performance computing systems based on single flux quantum logic. In this paper, a pulse control is designed to switch among stable equilibrium states of a Josephson junction array. Josephson junction arrays have the ability to store state information at low temperatures and energies, which naturally is useful for cryogenic memory applications. Although typical memory applications involve binary states, as a memory cell, the Josephson junction array has the ability to occupy nonbinary states given the nonlinear nature of the dynamics, which can lead to a reduced number of cells required in practical applications among other advantages. Transitions between states can be achieved through experimental testing for specific transitions, however, there are no known closed-form solutions to arbitrarily transition from one stable state to another. The system dynamics are similar to an array of coupled nonlinear oscillators, for which there is no known analytical solution. By providing an energy-based analysis for the junction array, a lower bound is determined and system trajectories are closely approximated such that the array is capable of transitioning between any desired stable equilibrium states under a Gaussian pulse input.
Josephson-junction interferometers have previously been proposed as memory devices in which information is stored as a single flux quantum, (SFQ). To investigate the feasibility of making large arrays of SFQ cells suitable for the memory of a cryogenic computer, arrays containing 80 interferometers have been made and measured. The prime objective was to determine the distribution of the dc Josephson current i1 within the arays and to compare it with the design value required for successful operation of all cells in high density arrays. The results show that a substantial fraction of the arrays has standard deviations in i1 less than the maximum allowable, thus demonstrating for the first time that such a memory can be made with present technology. The fabrication, measurement technique and a detailed analysis of the current distributions on the arrays are presented.