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Superconductor Science and Technology

Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

Niketh Nair, Amir Jafari-Salim, Anthony J. D’Addario, Neena Imam, Yehuda Y. Braiman

Published Sep 4, 2019• 15 citations
Publisher

Abstract

Abstract In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.

DOI
10.1088/1361-6668/ab416a

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Abstract In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.
Abstract In this paper we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.
The paper first summarizes requirements for a main memory with Josephson junctions and reviews the work carried out on an experimental main memory model containing an array of single-flux-quantum cells, line drivers, and address decoders with a total of nearly 4500 Josephson junctions. In the second part, theoretical and experimental investigations on the y drive system, including sense circuit, are presented. The investigations deal with both the read and write phases. Finally, the on-chip logic circuits and the address decoders are discussed, and the experimental results presented. Drivers and decoders based on the principle of current steering in superconducting loops are intended to be used on a fully populated main-memory chip.
The design and experimental results for a novel type of Josephson memory cell are presented. The cell has a simpler construction than the conventional Henkels-type, using a one-junction SQUID (superconducting quantum interference device) capacitively coupled to a single junction. Binary data are stored as single flux quanta and are destructively read out by sensing a pulse caused by a vortex-mode transition. Computer simulations suggest that the read operation could be performed with a bias margin for the sense junction of +or-28% and that the rise time of the sense current in a 16-bit memory cell would be as fast as 30 ps, despite having to sense a vortex-mode transition. Results are presented for a memory cell fabricated with Nb-AlO/sub x/-Nb junctions.>