A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.
A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation (2n+4 bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than 35W in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.
Gate-based quantum computers, poised to surpass their classical counterparts, drive intense research interest. Emulating quantum systems relies on state vector-type simulators, hampered by soaring memory demands, especially for systems beyond 40 qubits. Our solution called Trefoil system combines multiple FPGAs and SATA disks. Trefoil features a main unit and eight storage subsystems, each with 32 SATA disks, providing 2 PBytes of memory for up to 47 qubits. Sector-level block transfers enable efficient quantum operations such as H, Z, CNOT, and unitary matrices. The results show an H gate for 30 qubits executes in 10 minutes without increased times using parallel processing. Our study advances scalable quantum computing simulations, surmounting memory limitations.
Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we describe the design and empirical space/time complexity measurements of a working software prototype of a quantum computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main memory. We plan to prototype our design on a standard FPGA development board.
In response to the challenges in large-scale quantum state simulation on classical computing platforms, including memory limits, frequent disk I/O, and high computational complexity, this study builds upon a previously proposed hierarchical storage-based quantum simulation system and introduces an optimization framework, the Quantum Vector Optimization Framework (QVecOpt). QVecOpt integrates four strategies: amplitude pairing, cache optimization, block storage optimization, and parallel optimization. These collectively enhance state vector storage and computational scheduling. The amplitude pairing mechanism locates relevant amplitude pairs via bitwise XOR, reducing traversal complexity of single-qubit gates from O(2n) to O(1). Cache optimization pre-allocates buffers and loads only required data, cutting disk I/O. Block storage optimization partitions the state vector for on-demand loading and local updates, reducing redundant access. Parallel optimization distributes the state vector across nodes for collaborative computation, achieving near-linear speedup. Complexity analysis shows that, compared with hierarchical storage simulation, the method reduces state vector traversals for single-qubit gates from 2n to 1, removing the main bottleneck. It also lowers computational and I/O complexity from O(2n) to O(2n/C) and O(2n/B). In simulations of 16-29 qubits, efficiency improves nearly tenfold, breaking the memory bottleneck of existing tools and enabling high-bit quantum circuit simulations beyond traditional methods. This work provides an efficient, scalable solution for classical simulation of large-scale quantum computation with significant academic and practical value.
Software quantum simulators are the most accessible tools for designing and testing quantum algorithms. This paper presents a comprehensive approach to building a software-based quantum simulator based on classical computing architectures. We explore fundamental quantum computing concepts, including state vector representations, quantum gates, and memory management techniques. The simulator prototype implements various memory optimization strategies, such as full-state representation, dynamic state pruning, and shared memory parallelization with OpenMP and distributed memory models using MPI. Additionally, data compression techniques, like ZFP, are explored to enhance simulation performance by reducing memory footprint. The results are validated through performance comparisons with leading open-source quantum simulators, such as Intel-QS, QuEST, and qsim. Our findings highlight the trade-offs between computational overhead and memory efficiency. This demonstrates that a hybrid approach using distributed memory and compression offers the best scalability for simulating large quantum systems. This work provides a foundation for developing efficient quantum simulators supporting more complex quantum algorithms on classical hardware.