With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation $\left(2^{n+4}\right.$ bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than $35 \mathrm{~W}$ in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.
With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation (2n+4 bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than 35W in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
Gate-based quantum computers, poised to surpass their classical counterparts, drive intense research interest. Emulating quantum systems relies on state vector-type simulators, hampered by soaring memory demands, especially for systems beyond 40 qubits. Our solution called Trefoil system combines multiple FPGAs and SATA disks. Trefoil features a main unit and eight storage subsystems, each with 32 SATA disks, providing 2 PBytes of memory for up to 47 qubits. Sector-level block transfers enable efficient quantum operations such as H, Z, CNOT, and unitary matrices. The results show an H gate for 30 qubits executes in 10 minutes without increased times using parallel processing. Our study advances scalable quantum computing simulations, surmounting memory limitations.
A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
This study presents Q2SV, an FPGA‐based quantum state vector simulator implemented using high‐level synthesis (HLS), capable of simulating quantum circuits with up to 29 qubits. Using FPGA parallelism, efficient memory allocation, and hardware‐optimized execution pipelines, Q2SV achieves scalable quantum simulation without requiring iterative resynthesis. The system’s workflow processes OpenQASM circuits by providing a flexible and general‐purpose quantum state vector simulation approach. Experimental evaluations demonstrate significant reductions in execution time and storage requirements, positioning FPGAs as a possible alternative to GPUs and CPUs for large‐scale quantum circuit emulation. While not yet matching the raw computational power of high‐end CPUs and GPUs in all cases, this work establishes a foundational framework for future optimizations in hardware‐accelerated quantum simulation. This work provides an adaptable HLS‐based code that serves as a template that paves the way for enhanced memory management, parallel processing, and architecture‐specific optimizations, enabling more efficient FPGA‐based quantum simulations in the future.
As current trend of miniaturization in computing technology continues, modern computing devices would start to exhibit the behaviour of nanoscopic quantum objects. Quantum computing, which is based on the principles of quantum mechanics, becomes a promising candidate for future generation computing system. However, modelling quantum computing systems on existing classical computing platforms before the realization of viable large-scale quantum computer remains a major challenge. The exploration on the modelling of quantum computing systems on field programmable gate array (FPGA) platform, which offers the potential of massive parallelism and allows computational optimization at register-transfer level, is crucial. Due to the exponential growth of resource utilization with the increase in the number of quantum bits (qubit), existing works on modelling of quantum systems on FPGA platform are restricted to simple case studies using small qubit sizes. This work explores the modelling of quantum computing for emulation on FPGA platform based on two types of data structure: (a) state vector model and (b) Heisenberg model. For the conventional state vector modelling approach, an efficient datapath design that is based on serial-parallel hardware architecture, which allows resource sharing between unitary transformations, is proposed. Heisenberg model has been proven to be efficient in modelling stabilizer circuits, which are critical in error correction operations. In the effort to include the consideration of vital quantum error correction in practical quantum systems, a novel FPGA emulation framework that is based on the Heisenberg model is proposed. Effective algorithms for accurate global phase maintenance are proposed to facilitate the modelling of quantum systems based on the Heisenberg representation. The feasibility of the proposed state vector and Heisenberg emulation models are demonstrated based on a number of case studies with different characteristics, which include quantum Fourier transform, Grover’s search algorithm, and stabilizer circuits. Based on the state vector approach, this work has demonstrated the advantage of FPGA emulation over software simulation where hardware emulation of 7-qubit Grover’s search is about 3 × 104 times faster than the software simulation performed on Intel Core i7-4790 processor running at 3.6GHz clock rate. In contrast to the 8-qubit implementation based on the state vector model, the proposed FPGA emulation framework based on the Heisenberg model has successfully modelled 120-qubit stabilizer circuits on the Altera Stratix IV FPGA. In summary, the proposed work in this thesis contributes to the formulation of a proof-of-concept of efficient FPGA emulation framework based on the state vector and Heisenberg models.