Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International Conference on Field-Programmable Technology (FPT)

Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages

Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi

Published Dec 12, 2023• 1 citation
Publisher

Abstract

Gate-based quantum computers, poised to surpass their classical counterparts, drive intense research interest. Emulating quantum systems relies on state vector-type simulators, hampered by soaring memory demands, especially for systems beyond 40 qubits. Our solution called Trefoil system combines multiple FPGAs and SATA disks. Trefoil features a main unit and eight storage subsystems, each with 32 SATA disks, providing 2 PBytes of memory for up to 47 qubits. Sector-level block transfers enable efficient quantum operations such as H, Z, CNOT, and unitary matrices. The results show an H gate for 30 qubits executes in 10 minutes without increased times using parallel processing. Our study advances scalable quantum computing simulations, surmounting memory limitations.

DOI
10.1109/icfpt59805.2023.00049

Related papers

Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages

Kaijie Wei, Hideharu Amano, Ryohei Niwase +2 more

Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with $n$ qubits requires $2^{n+4}$ bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.

quant-pharXiv:2608.14285•IEEE Transactions on Computers•Aug 17, 2026•9 citations

A state vector quantum simulator working on FPGAs with extensible SATA storage

Kaijie Wei, Ryohei Niwase, Hideharu Amano +2 more

With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation $\left(2^{n+4}\right.$ bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than $35 \mathrm{~W}$ in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.

International Conference on Field-Programmable Technology (FPT)•Dec 12, 2023•4 citations

A data compressor for FPGA-based state vector quantum simulators

Kaijie Wei, Amano Hideharu, Ryohei Niwase +1 more

A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.

International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)•Jun 17, 2024•4 citations

FPGA Based Quantum Circuit Simulator: Processing 30 Qubit Systems

Nasir Ali Nasir Ali, Anupam Tiwari, Nadeem khan Nadeem khan +5 more

Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.

•Jan 20, 2026•1 citation

Theoretical Analysis of the Memory-Efficient Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs

Le Tran Xuan Hieu, Pham Hoai Luan, Vu Tuan Hai +2 more

Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the MEMS (Memory-Efficient Matrix Storage) method for storing quantum operators and states, along with a MEMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the MEMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 22to 25on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it substantially faster than previous works.

IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)•Dec 16, 2024•3 citations

Theoretical Analysis of the Efficient-Memory Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs

Thuyen Le, Hoai Luan Pham, Vu Tuan Hai +2 more

Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the EMMS (Efficient-Memory Matrix Storage) method for storing quantum operators and states, along with an EMMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the EMMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from $2^2$ to $2^5$ on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it significantly faster than previous works.

arXiv:2410.11146•Oct 15, 2024•0 citations
Gate-based quantum computers, poised to surpass their classical counterparts, drive intense research interest. Emulating quantum systems relies on state vector-type simulators, hampered by soaring memory demands, especially for systems beyond 40 qubits. Our solution called Trefoil system combines multiple FPGAs and SATA disks. Trefoil features a main unit and eight storage subsystems, each with 32 SATA disks, providing 2 PBytes of memory for up to 47 qubits. Sector-level block transfers enable efficient quantum operations such as H, Z, CNOT, and unitary matrices. The results show an H gate for 30 qubits executes in 10 minutes without increased times using parallel processing. Our study advances scalable quantum computing simulations, surmounting memory limitations.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with nnn qubits requires 2n+42^{n+4}2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation (2n+4\left(2^{n+4}\right.(2n+4 bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than 35 W35 \mathrm{~W}35 W in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.
A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the MEMS (Memory-Efficient Matrix Storage) method for storing quantum operators and states, along with a MEMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the MEMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 22to 25on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it substantially faster than previous works.
Quantum emulators play an important role in the development and testing of quantum algorithms, especially given the limitations of the current FTQC era. Developing high-speed, memory-optimized quantum emulators is a growing research trend, with gate fusion being a promising technique. However, existing gate fusion implementations often struggle to efficiently support large-scale quantum systems with a high number of qubits due to a lack of optimizations for the exponential growth in memory requirements. Therefore, this study proposes the EMMS (Efficient-Memory Matrix Storage) method for storing quantum operators and states, along with an EMMS-based Quantum Emulator Accelerator (QEA) architecture that incorporates multiple processing elements (PEs) to accelerate tensor product and matrix multiplication computations in quantum emulation with gate fusion. The theoretical analysis of the QEA on the Xilinx ZCU102 FPGA, using varying numbers of PEs and different depths of unitary and local data memory, reveals a linear increase in memory depth with the number of qubits. This scaling highlights the potential of the EMMS-based QEA to accommodate larger quantum circuits, providing insights into selecting appropriate memory sizes and FPGA devices. Furthermore, the estimated performance of the QEA with PE counts ranging from 222^222 to 252^525 on the Xilinx ZCU102 FPGA demonstrates that increasing the number of PEs significantly reduces the computation cycle count for circuits with fewer than 18 qubits, making it significantly faster than previous works.