Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we describe the design and empirical space/time complexity measurements of a working software prototype of a quantum computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main memory. We plan to prototype our design on a standard FPGA development board.
Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we describe the design and empirical space/time complexity measurements of a working software prototype of a quantum computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main memory. We plan to prototype our design on a standard FPGA development board.
A quantum computer simulator is a tool that simulates the operation of a quantum computer using classical computers. Researchers widely adopt the state-vector-based simulator to reproduce the state of quantum bits (qubits) faithfully. A challenge arises in requiring a main memory space of 2n + 4 bytes to handle n quantum bits. Considering power efficiency and cost, we propose implementing a quantum computer simulator named Qu-Trefoil using Serial ATA (SATA) disks directly connected to an FPGA board called Trefoil. Due to the limited data transfer speed between SATA disks and FPGA, improving the overall system performance is challenging. This study proposes improving the overall system throughput using data compression. Considering the data characteristics in the state vector method and the overall system structure, we verify that we can eliminate the communication bottleneck on the host side of Trefoil by employing the floating-point compression algorithm ZFP based on FPGA. Focusing on the compression aspect in Trefoil, this paper elucidates the bottlenecks of the target system and conducts implementation and evaluation. Moreover, by utilizing partially optimized compression IP, it is possible to achieve performance nearly four times higher than the original design, resulting in a throughput of 3.7GB/s, comparable with the benchmark ZFP working on CPU devices. Optimizing the entire IP can potentially improve the overall simulator’s performance.
With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation (2n+4 bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than 35W in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.
As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Software quantum simulators are the most accessible tools for designing and testing quantum algorithms. This paper presents a comprehensive approach to building a software-based quantum simulator based on classical computing architectures. We explore fundamental quantum computing concepts, including state vector representations, quantum gates, and memory management techniques. The simulator prototype implements various memory optimization strategies, such as full-state representation, dynamic state pruning, and shared memory parallelization with OpenMP and distributed memory models using MPI. Additionally, data compression techniques, like ZFP, are explored to enhance simulation performance by reducing memory footprint. The results are validated through performance comparisons with leading open-source quantum simulators, such as Intel-QS, QuEST, and qsim. Our findings highlight the trade-offs between computational overhead and memory efficiency. This demonstrates that a hybrid approach using distributed memory and compression offers the best scalability for simulating large quantum systems. This work provides a foundation for developing efficient quantum simulators supporting more complex quantum algorithms on classical hardware.