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ACM Great Lakes Symposium on VLSI (GLSVLSI)

A New Routing Strategy to Improve Success Rates of Quantum Computers

Fang Qi, Xin Fu, Xu Yuan, Nian-Feng Tzeng, Lu Peng

Published Jun 10, 2024• 1 citation
Publisher

Abstract

In the current noisy intermediate-scale quantum (NISQ) Era, Quantum Computing faces significant challenges due to noise, which severely restricts the application of computing complex algorithms. Superconducting quantum chips, one of the pioneer quantum computation technologies, introduce additional noise when moving qubits to adjacent locations for operation on designated two-qubit gates. The current compilers rely on decision models that either count the swap gates or multiply the gate errors when choosing swap paths at the routing stage. Our research has unveiled the overlooked situations for error propagations through the circuit, leading to accumulations that may affect the final output.

DOI
10.1145/3649476.3658790

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In the current noisy intermediate-scale quantum (NISQ) Era, Quantum Computing faces significant challenges due to noise, which severely restricts the application of computing complex algorithms. Superconducting quantum chips, one of the pioneer quantum computation technologies, introduce additional noise when moving qubits to adjacent locations for operation on designated two-qubit gates. The current compilers rely on decision models that either count the swap gates or multiply the gate errors when choosing swap paths at the routing stage. Our research has unveiled the overlooked situations for error propagations through the circuit, leading to accumulations that may affect the final output.
Quantum computing in the Noisy Intermediate-Scale Quantum (NISQ) era faces significant challenges due to the limitations in quantum gate fidelity and elevated error rates, which impede the successful execution of large-scale quantum circuits. One major source of errors in quantum computing is ’coherence errors’, which arise from the idle time during circuit execution. Specifically, factors such as uneven gate operations, hardware limitations, and qubit connectivity constraints collectively contribute to the formation of ’holes’ in quantum circuits, leading to ’idle qubits’. These idle periods, in turn, increase noise and error rates, thus negatively impacting the overall reliability of quantum circuits’ outputs.
Routing plays an important role in programming noisy, intermediate-scale quantum (NISQ) devices, where limited connectivity in the register is overcome by swapping quantum information between locations. However, routing a quantum state using noisy gates introduces non-trivial noise dynamics, and deciding on an optimal route to minimize accumulated error requires estimates of the expected state fidelity. Here we validate a model for state-dependent routing dynamics in a NISQ processor based on correlated binary noise. We develop a composable, state-dependent noise model for CNOT and SWAP operations that can be characterized efficiently using pair-wise experimental measurements, and we compare model predictions with tomographic state reconstructions recovered from a quantum device. These results capture the state-dependent routing dynamics that are needed to guide routing decisions for near-real time operation of NISQ devices.
Quantum computing is a quickly growing field with great potential for future technology. Quantum computers in the current noisy intermediate-scale quantum (NISQ) era face two major limitations - qubit count and error vulnerability. Although quantum error correction (QEC) methods exist, they are not applicable to the current size of computers, requiring thousands of qubits, while current NISQ systems have hundreds at most. It is therefore imperative to improve the reliability of the circuits as much as possible to make them robust to the errors that will occur. One common approach is to adjust the compilation process of a circuit to create a final circuit with improved reliability. However, there are many decisions to be made when compiling that affect the final performance of the circuit, two of the most critical ones being the mapping of logical to physical qubits (the qubit allocation problem) and the movement of qubits to satisfy two-qubit gate adjacency requirements (the qubit routing problem). We focus on solving the qubit allocation problem and identifying initial layouts that reduce error. To identify these layouts, we combine reinforcement learning with a graph neural network (GNN)-based Q-network for analyzing both the connections and error rates of the graph-like backend of superconducting quantum computers to make mapping decisions, creating a Graph Neural Network Assisted Compilation (GNAQC) strategy. We provide both the circuit and the properties of the target backend as input to guide the decision-making process. We work with the IBM Qiskit API to compile and simulate our quantum circuits. We train the architecture using a set of four backends and six circuits and find that GNAQC generally outperforms pre-existing qubit allocation algorithms, increasing final relative output fidelity by roughly 12.7%.
Optimizing quantum circuits is a critical step in the design and deployment of efficient, scalable, and fault tolerant quantum algorithms. As quantum circuits grow in depth and complexity, they often accumulate redundant or unnecessary gate operations. These redundancies not only increase the resource requirements of the circuit but also exacerbate one of the most pressing challenges in quantum computing—quantum noise. Unlike classical noise, quantum noise can irreversibly disturb the fragile quantum state, leading to decoherence and erroneous computational outcomes.
Despite the current progress in quantum computing, the reliability of quantum computers is very challenging. Near-term quantum computers referred to as Noisy Intermediate-Scale Quantum (NISQ) computers are expected to operate in the presence of errors. To run a quantum circuit on a NISQ computer, the circuit should be mapped to satisfy the physical constraints of the quantum architecture. The mapping process takes into account the error rates of the quantum hardware. It selects physical qubits and their movements, which minimize the circuit error rates. The output of the quantum circuit can be obtained through several runs on NISQ computers.
Quantum computing promises breakthroughs in simulating and solving complex, classically intractable problems. However, current noisy intermediate-scale quantum (NISQ) devices are relatively small and error-prone, prohibiting large-scale computations. To achieve quantum advantage in this regime, it is crucial to minimise the impact of noise from qubit decoherence and two-qubit gates. A direct approach is to optimise quantum circuit compilation, particularly by improving how circuits are mapped onto hardware. This work targets multi-qubit pathfinding (MQPF), a key subproblem in quantum circuit mapping, formulated as a variant of the token swapping problem. We propose an adaptable algorithm, modelled as a binary integer linear program, that routes KKK teams of qubits on hardware graphs using swap operations. The algorithm minimises SWAP-gate depth and accumulated gate and idle errors, effectively solving a weighted version of the parallel (K+1K+1K+1)-coloured token swapping problem. We benchmark performance across various hardware layouts, comparing runtimes, SWAP depths, gate counts, and errors. Our results show that the proposed MQPF algorithm offers significantly improved runtime scaling and lower accumulated errors over a state-of-the-art exact SMT-CBS-based method. Potential applications include precomputing optimal routing for circuit mappers, benchmarking heuristics, and informing quantum hardware design by analysing pathfinding behaviour.