This work presents a routing-aware pruning strategy for quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) devices. We propose a method to remove parametric controlled rotations whose small rotation angles do not justify the routing overhead required for their implementation. By selectively pruning such gates, the method mitigates fidelity loss arising from additional SWAP operations introduced during compilation. Our approach evaluates whether executing a gate leads to greater fidelity loss than omitting it. Simulations on benchmark circuits with realistic noise models show that the method reduces two-qubit gate counts (up to 48.6%) while improving final state fidelity (up to 47.7%), especially for larger circuits where routing costs dominate.
This work presents a routing-aware pruning strategy for quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) devices. We propose a method to remove parametric controlled rotations whose small rotation angles do not justify the routing overhead required for their implementation. By selectively pruning such gates, the method mitigates fidelity loss arising from additional SWAP operations introduced during compilation. Our approach evaluates whether executing a gate leads to greater fidelity loss than omitting it. Simulations on benchmark circuits with realistic noise models show that the method reduces two-qubit gate counts (up to 48.6%) while improving final state fidelity (up to 47.7%), especially for larger circuits where routing costs dominate.
We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to 84% higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.
Quantum circuit routing is a key step in compiling programs for noisy intermediate-scale quantum processors, particularly superconducting devices whose sparse fixed coupling makes routing a central compilation cost. Routes that appear efficient by standard overhead metrics such as SWAP count, routed two-qubit count, and depth can still lose fidelity when they pass through poorly calibrated couplers. We study a calibration-aware graph reinforcement-learning router that uses same-day calibration data from superconducting IBM Heron r2 processors to choose hardware-edge SWAPs. We train the policy with proximal policy optimization and evaluate it with exact simulated fidelity across nine Munich Quantum Toolkit (MQT) Bench circuits and three calibration snapshots. Across these evaluations, pooled mean exact fidelity is 0.727, compared with 0.440 for SWAP-based bidirectional heuristic search (SABRE)-best20 and 0.481 for target-aware SABRE. We observe that fidelity gains come with higher routed two-qubit counts and are concentrated in 5 qubit and 8 qubit circuit families; under the fixed tree action graph, all 10 qubit families favor SABRE-best20. Overall, our results show that calibration-aware learned routing can improve fidelity beyond gate-count-driven compilation, by roughly 0.25 to 0.29 in absolute mean fidelity over the SABRE-family baselines.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale.
In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
In the current noisy intermediate-scale quantum (NISQ) Era, Quantum Computing faces significant challenges due to noise, which severely restricts the application of computing complex algorithms. Superconducting quantum chips, one of the pioneer quantum computation technologies, introduce additional noise when moving qubits to adjacent locations for operation on designated two-qubit gates. The current compilers rely on decision models that either count the swap gates or multiply the gate errors when choosing swap paths at the routing stage. Our research has unveiled the overlooked situations for error propagations through the circuit, leading to accumulations that may affect the final output.