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EPJ Quantum Technology

Full quantum tomography study of Google’s Sycamore gate on IBM’s quantum computers

M. AbuGhanem, Hichem Eleuch

Published May 27, 2024• 31 citations
Publisher

Abstract

Abstract The potential of achieving computational hardware with quantum advantage depends heavily on the quality of quantum gate operations. However, the presence of imperfect two-qubit gates poses a significant challenge and acts as a major obstacle in developing scalable quantum information processors. Google’s Quantum AI and collaborators claimed to have conducted a supremacy regime experiment. In this experiment, a new two-qubit universal gate called theSycamoregate is constructed and employed to generate random quantum circuits (RQCs), using a programmable quantum processor with 53 qubits. These computations were carried out in a computational state space of size $9 \times 10^{15}$ 9×1015 . Nevertheless, even in strictly-controlled laboratory settings, quantum information on quantum processors is susceptible to various disturbances, including undesired interaction with the surroundings and imperfections in the quantum state. To address this issue, we conduct both quantum state tomography (QST) and quantum process tomography (QPT) experiments on Google’sSycamoregate using different artificial architectural superconducting quantum computer. Furthermore, to demonstrate how errors affect gate fidelity at the level of quantum circuits, we design and conduct full QST experiments for the five-qubit eight-cycle circuit, which was introduced as an example of the programability of Google’sSycamorequantum processor. These quantum tomography experiments are conducted in three distinct environments: noise-free, noisy simulation, and on IBM Quantum’s genuine quantum computer. Our results offer valuable insights into the performance of IBM Quantum’s hardware and the robustness ofSycamoregates within this experimental setup. These findings contribute to our understanding of quantum hardware performance and provide valuable information for optimizing quantum algorithms for practical applications.

DOI
10.1140/epjqt/s40507-024-00248-8

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Abstract The potential of achieving computational hardware with quantum advantage depends heavily on the quality of quantum gate operations. However, the presence of imperfect two-qubit gates poses a significant challenge and acts as a major obstacle in developing scalable quantum information processors. Google’s Quantum AI and collaborators claimed to have conducted a supremacy regime experiment. In this experiment, a new two-qubit universal gate called theSycamoregate is constructed and employed to generate random quantum circuits (RQCs), using a programmable quantum processor with 53 qubits. These computations were carried out in a computational state space of size 9×10159 \times 10^{15}9×1015 9×1015 . Nevertheless, even in strictly-controlled laboratory settings, quantum information on quantum processors is susceptible to various disturbances, including undesired interaction with the surroundings and imperfections in the quantum state. To address this issue, we conduct both quantum state tomography (QST) and quantum process tomography (QPT) experiments on Google’sSycamoregate using different artificial architectural superconducting quantum computer. Furthermore, to demonstrate how errors affect gate fidelity at the level of quantum circuits, we design and conduct full QST experiments for the five-qubit eight-cycle circuit, which was introduced as an example of the programability of Google’sSycamorequantum processor. These quantum tomography experiments are conducted in three distinct environments: noise-free, noisy simulation, and on IBM Quantum’s genuine quantum computer. Our results offer valuable insights into the performance of IBM Quantum’s hardware and the robustness ofSycamoregates within this experimental setup. These findings contribute to our understanding of quantum hardware performance and provide valuable information for optimizing quantum algorithms for practical applications.
Abstract Characterizing quantum dynamics is critical in quantum physics, quantum information science, and computation, where the precision of quantum gates plays a key role. We present a comprehensive experimental analysis of the SQSCZ gate–a novel universal two-qubit entangling gate combining SWAP\sqrt{\text {SWAP}}SWAP​ SWAP and CZ\sqrt{\text {CZ}}CZ​ CZ operations–on superconducting quantum hardware. Leveraging quantum process tomography via the Choi-Jamiołkowski isomorphism, we benchmark the gate’s performance across different noise environments. Experimental results demonstrate high process fidelities of 97.27%97.27\%97.27% 97.27 % (quantum simulator) and 88.99%88.99\%88.99% 88.99 % (quantum hardware), revealing remarkable noise resilience. Owing to its hybrid architecture, circuit depth reduction capabilities, and hardware-efficient decomposition into only two CNOT gates, the SQSCZ gate holds strong potential for near-term quantum applications, including the Quantum Fourier Transform and Variational Quantum Eigensolvers for molecular simulations. These findings establish the SQSCZ gate as a promising primitive for NISQ-era quantum algorithms, while providing key insights into gate-level error processes in superconducting quantum processors.
Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.
Abstract We present an experimental characterization of the three-qubit controlled-controlled-Z (CCZ) gate on IBM Quantum’s 127-qubit superconducting quantum computers, revealing state-backend-dependent performance variations. Using quantum state tomography (QST), we evaluate the gate’s output-state fidelity when applied to three algorithmically significant input states—the W state, the Greenberger–Horne–Zeilinger (GHZ) state, and the uniform superposition state. Each state probes distinct aspects of the reconstructed state fidelity, the GHZ state tests coherence in maximally entangled systems, the W state reveals sensitivity to asymmetric errors, and the uniform superposition assesses basis-state-independent behavior. Experiments were conducted across three computational environments, noise-free simulation, noisy simulation, and actual hardware executions on three IBM Quantum computers, ibm_osaka , ibm_brisbane , and ibm_sherbrooke . State fidelities for the qasm_simulator remained above 99.2% for all input states. Noisy simulations yielded fidelities around 80–82%, while hardware results showed more significant degradation: 67.6% (GHZ), 59.0% (uniform superposition), and 50.3% (W)—highlighting the combined importance of state selection and hardware characteristics for reliable quantum computation. These results quantify the current performance gap between simulated and physical implementations of multi-qubit gates and provide a benchmark for error profiles relevant to near-term quantum algorithms
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
This study aims to analyze recent developments in quantum supremacy by comparing the computational performance of stabilized superconducting qubit systems with classical supercomputing capabilities. A systematic literature review was conducted on major experimental studies published between 2019 and 2024, focusing on random circuit sampling, qubit stability, gate fidelity, and computational runtime comparisons. The analysis covers key quantum processors, including Sycamore and Zuchongzhi, by evaluating three main parameters: number of qubits, circuit complexity, and performance gap relative to classical simulation.The results show that quantum processors with 50–100 qubits and high gate fidelity are able to complete specific sampling tasks within seconds to hours, whereas equivalent classical simulations would require thousands to billions of years. The findings also indicate that computational advantage increases exponentially with system scale and is strongly influenced by qubit stability and error suppression techniques. Although the demonstrated tasks remain specialized and not yet applicable to practical problems, the evidence confirms that stabilized qubit systems have achieved a measurable computational regime beyond classical feasibility.This review provides a clear synthesis of current experimental achievements and highlights that future progress toward practical quantum advantage depends on improvements in error correction, scalability, and hardware reliability.
Quantum state tomography (QST) is a fundamental technique for characterizing quantum states, traditionally employed in research laboratories with highly controlled environments. However, the burgeoning field of quantum computing faces the significant challenge of deploying and verifying quantum hardware in the presence of noise and decoherence, characteristics inherent in current Noisy Intermediate-Scale Quantum (NISQ) devices. This paper proposes an adapted QST algorithm designed to overcome these limitations. The core idea is to systematically reconstruct the density matrix of a qubit or a small quantum system using a series of carefully designed measurements. We address the impact of noise by incorporating error mitigation strategies within the reconstruction process. The algorithm's performance is evaluated through theoretical analysis and conceptual implementation, highlighting its potential to provide a practical and efficient method for hardware verification of NISQ computers. This work establishes a novel approach for characterizing and debugging NISQ hardware, a critical step toward realizing the full potential of quantum computation.