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Scientific Reports

State-backend-dependent fidelity of the CCZ gate on superconducting quantum computers

M. AbuGhanem

Published Oct 12, 2026• 0 citations
Publisher

Abstract

Abstract We present an experimental characterization of the three-qubit controlled-controlled-Z (CCZ) gate on IBM Quantum’s 127-qubit superconducting quantum computers, revealing state-backend-dependent performance variations. Using quantum state tomography (QST), we evaluate the gate’s output-state fidelity when applied to three algorithmically significant input states—the W state, the Greenberger–Horne–Zeilinger (GHZ) state, and the uniform superposition state. Each state probes distinct aspects of the reconstructed state fidelity, the GHZ state tests coherence in maximally entangled systems, the W state reveals sensitivity to asymmetric errors, and the uniform superposition assesses basis-state-independent behavior. Experiments were conducted across three computational environments, noise-free simulation, noisy simulation, and actual hardware executions on three IBM Quantum computers, ibm_osaka , ibm_brisbane , and ibm_sherbrooke . State fidelities for the qasm_simulator remained above 99.2% for all input states. Noisy simulations yielded fidelities around 80–82%, while hardware results showed more significant degradation: 67.6% (GHZ), 59.0% (uniform superposition), and 50.3% (W)—highlighting the combined importance of state selection and hardware characteristics for reliable quantum computation. These results quantify the current performance gap between simulated and physical implementations of multi-qubit gates and provide a benchmark for error profiles relevant to near-term quantum algorithms

DOI
10.1038/s41598-026-71155-4

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Abstract We present an experimental characterization of the three-qubit controlled-controlled-Z (CCZ) gate on IBM Quantum’s 127-qubit superconducting quantum computers, revealing state-backend-dependent performance variations. Using quantum state tomography (QST), we evaluate the gate’s output-state fidelity when applied to three algorithmically significant input states—the W state, the Greenberger–Horne–Zeilinger (GHZ) state, and the uniform superposition state. Each state probes distinct aspects of the reconstructed state fidelity, the GHZ state tests coherence in maximally entangled systems, the W state reveals sensitivity to asymmetric errors, and the uniform superposition assesses basis-state-independent behavior. Experiments were conducted across three computational environments, noise-free simulation, noisy simulation, and actual hardware executions on three IBM Quantum computers, ibm_osaka , ibm_brisbane , and ibm_sherbrooke . State fidelities for the qasm_simulator remained above 99.2% for all input states. Noisy simulations yielded fidelities around 80–82%, while hardware results showed more significant degradation: 67.6% (GHZ), 59.0% (uniform superposition), and 50.3% (W)—highlighting the combined importance of state selection and hardware characteristics for reliable quantum computation. These results quantify the current performance gap between simulated and physical implementations of multi-qubit gates and provide a benchmark for error profiles relevant to near-term quantum algorithms
Abstract Generating and detecting genuine multipartite entanglement (GME) of sizeable quantum states prepared on physical devices is an important benchmark for highlighting the progress of near-term quantum computers. A common approach to certify GME is to prepare a Greenberger-Horne-Zeilinger (GHZ) state and measure a GHZ fidelity of at least 0.5. We measure the fidelities using multiple quantum coherences of GHZ states on 11 to 27 qubits prepared on the IBM Quantum ibmq_montreal device. Combinations of quantum readout error mitigation (QREM) and parity verification error detection are applied to the states. A fidelity of 0.546 ± 0.017 was recorded for a 27-qubit GHZ state when QREM was used, demonstrating GME across the full device with a confidence level of 98.6%. We benchmarked the effect of parity verification on GHZ fidelity for two GHZ state preparation embeddings on the heavy-hexagon architecture. The results show that the effect of parity verification, while relatively modest, led to a detectable improvement of GHZ fidelity.
The development of complex circuits for practical applications in the current quantum computing ecosystem is based on basic primitives such as Bell states, which provide superposition, entanglement, and coherence. The range of domain-specific quantum applications has been greatly expanded by the availability of simulators and platforms such as IBM Quantum, which are supported by Qiskit. However, disparities between ideal simulator outputs and actual quantum processing unit (QPU) executions in the Noisy Intermediate-Scale Quantum (NISQ) era require the application of quantum error mitigation techniques. Limitations arise from hardware constraints in superconducting qubit systems and from the limited resources of classical simulators as quantum circuits grow. Quantum decoherence, which lowers gate fidelity and builds up at the circuit level with increasing depth, is specifically caused by material-induced flaws and interfaces. This creates a clear connection between circuit reliability, device performance, and material attributes. To address this, the current work uses both simulation and actual hardware on the IBM Sherbrooke 127-qubit processor to study three basic circuit classes over 4 to 10 qubits: the quantum Fourier transform, the Greenberger-Horne-Zeilinger state, and the W state. The study examines trade-offs between circuit complexity, noise robustness, and resource utilization by contrasting simulator and QPU results. The results imply that circuit fidelity can serve as an indirect probe of material-limited noise, opening the door to a framework for designing quantum circuits that accounts for both hardware and materials to achieve scalable quantum advantage.
Noisy intermediate-scale quantum computers (NISQ) have demonstrated superior performance compared to conventional computing schemes. Nonetheless, errors associated with two-qubit entangling gates remain a substantial obstacle in fully harnessing the potential of current superconducting quantum computers. The achievement of quantum computation and quantum information processing critically depends on the presence of entangled states. These states are indispensable for quantum computers to surpass classical computers in terms of computational power. This paper presents a comprehensive characterization of a two-qubit entangling gate, known as Dagwood Bumstead (DB) gate, to investigate the challenges posed by errors in the DB gate on NISQ devices. Firstly, we propose a scheme for the realization of the DB gate using two capacitively coupled Josephson Superconducting qubits, based on the experimental setup carried out in Bialczak et al. (2010). The gate’s performance is fully described through quantum process tomography (QPT) and quantum state tomography (QST) experiments conducted in three different environments: noisy, noiseless, and on a real IBM quantum computer. The process fidelity of the DB gate is measured to be 0.8069705, and the state fidelity is determined to be 0.8858750. This study offers valuable insights into the performance of the DB gate on a NISQ device, showcasing its potential for executing intricate algorithms and operations on an authentic quantum computer.
Abstract While all quantum algorithms can be expressed in terms of single-qubit and two-qubit gates, more expressive gate sets can help reduce the algorithmic depth. This is important in the presence of gate errors, especially those due to decoherence. Using superconducting qubits, we have implemented a three-qubit gate by simultaneously applying two-qubit operations, thereby realizing a three-body interaction. This method straightforwardly extends to other quantum hardware architectures, requires only a firmware upgrade to implement, and is faster than its constituent two-qubit gates. The three-qubit gate represents an entire family of operations, creating flexibility in the quantum-circuit compilation. We demonstrate a process fidelity of 97.90%, which is near the coherence limit of our device. We then generate two classes of entangled states, the Greenberger–Horne–Zeilinger and Dicke states, by applying the new gate only once; in comparison, decompositions into the standard gate set would have a two-qubit gate depth of two and three, respectively. Finally, we combine characterization methods and analyze the experimental and statistical errors in the fidelity of the gates and of the target states.
Quantum devices in the noisy intermediate-scale quantum (NISQ) era are highly susceptible to different types of quantum noise, which directly impact the reliability of experimental results. This work provides a characterization of error behavior arising from quantum noises on IBM's superconducting quantum processor, offering practical insights for algorithm design, benchmarking, and error-mitigation strategies on a real superconducting quantum processor in the NISQ era. The study begins with the measurement of the basis state, without applying any gate, to quantify state-preparation and measurement (SPAM) errors. Additionally, the errors are further quantified due to the application of single-qubit Pauli-X, two-qubit CNOT gate and other multi-qubit Controlled-X gates. Each circuit was executed with 1024 shots, and the percentage error between the expected and observed outputs was computed. The results show that the single-qubit Pauli-X gate exhibits relatively low errors in comparison with the two-qubit CNOT gate, whereas other multi-qubit Controlled-X gates lead to significantly higher deviations. This work also analyzes the noise effect of a fourqubit Controlled-X gate being implemented using a three-qubit Controlled-X gate with an extra auxiliary qubit, and the result shows a significant reduction in the error rate.
Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of FpCX=93.02%\mathcal {F}_p^{\text {CX}} = 93.02\%FpCX​=93.02% F p CX = 93.02 % and correctly prepared the target state with P00CX=92.40%P_{00}^{\text {CX}} = 92.40\%P00CX​=92.40% P 00 CX = 92.40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved FpCZ=92.59%\mathcal {F}_p^{\text {CZ}} = 92.59\%FpCZ​=92.59% F p CZ = 92.59 % with superior state-preparation fidelity of P00CZ=97.08%P_{00}^{\text {CZ}} = 97.08\%P00CZ​=97.08% P 00 CZ = 97.08 % . Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4.68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.