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Scientific Reports

Design of high-performance entangling logic in silicon quantum dot systems with Bayesian optimization

Ji-Hoon Kang, Taehyun Yoon, Chanhui Lee, Sungbin Lim, Hoon Ryu

Published May 2, 2024• 3 citations
Publisher

Abstract

Device engineering based on computer-aided simulations is essential to make silicon (Si) quantum bits (qubits) be competitive to commercial platforms based on superconductors and trapped ions. Combining device simulations with the Bayesian optimization (BO), here we propose a systematic design approach that is quite useful to procure fast and precise entangling operations of qubits encoded to electron spins in electrode-driven Si quantum dot (QD) systems. For a target problem of the controlled-X (CNOT) logic operation, we employ BO with the Gaussian process regression to evolve design factors of a Si double QD system to the ones that are optimal in terms of speed and fidelity of a CNOT logic driven by a single microwave pulse. The design framework not only clearly contributes to cost-efficient securing of solutions that enhance performance of the target quantum operation, but can be extended to implement more complicated logics with Si QD structures in experimentally unprecedented ways.

DOI
10.1038/s41598-024-60478-9

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Scientific Reports•Sep 30, 2021•28 citations
Device engineering based on computer-aided simulations is essential to make silicon (Si) quantum bits (qubits) be competitive to commercial platforms based on superconductors and trapped ions. Combining device simulations with the Bayesian optimization (BO), here we propose a systematic design approach that is quite useful to procure fast and precise entangling operations of qubits encoded to electron spins in electrode-driven Si quantum dot (QD) systems. For a target problem of the controlled-X (CNOT) logic operation, we employ BO with the Gaussian process regression to evolve design factors of a Si double QD system to the ones that are optimal in terms of speed and fidelity of a CNOT logic driven by a single microwave pulse. The design framework not only clearly contributes to cost-efficient securing of solutions that enhance performance of the target quantum operation, but can be extended to implement more complicated logics with Si QD structures in experimentally unprecedented ways.
The quality of quantum bits (qubits) in silicon is highly vulnerable to charge noise that is omnipresent in semiconductor devices and is in principle hard to be suppressed. For a realistically sized quantum dot system based on a silicon-germanium heterostructure whose confinement is manipulated with electrical biases imposed on top electrodes, we computationally explore the noise-robustness of 2-qubit entangling operations with a focus on the controlled-X (CNOT) logic that is essential for designs of gate-based universal quantum logic circuits. With device simulations based on the physics of bulk semiconductors augmented with electronic structure calculations, we not only quantify the degradation in fidelity of single-step CNOT operations with respect to the strength of charge noise, but also discuss a strategy of device engineering that can significantly enhance noise-robustness of CNOT operations with almost no sacrifice of speed compared to the single-step case. Details of device designs and controls that this work presents can establish practical guideline for potential efforts to secure silicon-based quantum processors using an electrode-driven quantum dot platform.
Silicon spin qubits are a promising platform for large-scale quantum computing because of their compatibility with advanced semiconductor fabrication technology. However, charge noise remains a major challenge since it causes timedependent drifts in qubit frequency and exchange interactions through electric field fluctuations. These drifts in control parameters are one obstacle to achieving the high-fidelity quantum operations required for quantum error correction. In this work, we propose a Bayesian optimization (BO) framework for the adaptive calibration of quantum gate parameters in silicon qubits. In addition, to address the impact of charge noise, which exhibits a1/f1 / f1/f-like power spectral density, we incorporate a forgetting mechanism into the Gaussian process model used during optimization. Our simulations on a realistic silicon quantum dot system show that BO-based method improves gate fidelity by 0.266% and reduces calibration iterations by 36.9% compared to random search. Compared to standard BO, our modified method achieves a further fidelity gain of 0.008% and a 9.23% reduction in iterations. These results highlight the potential of BO-based calibration for robust quantum gate implementation under realistic noise conditions.
With recent experimental advancements demonstrating high-fidelity universal logic gates and basic programmability, silicon-based spin quantum bits (qubits) have emerged as promising candidates for scalable quantum computing. However, implementation of more complex quantum information protocols with many qubits still remains a critical challenge for realization of practical programmability in silicon devices. In this study, we present a computational investigation of entanglement-based quantum information applications implemented on an electrically defined quantum dot structure in silicon. Using in-house multi-scale simulations based on tight-binding calculations augmented with classical physics with bulk properties, we model a five quantum dot system that can create up to five electron spin qubits, and discuss details of control engineering needed to implement single-qubit rotations and two-qubit logic operations in a programmable manner. Using these elementary operations, we design a five-qubit quantum teleportation protocol and computationally verify its end-to-end operation including a simple but clear analysis on how the designed circuit can be affected by charge noise. With engineering details that are not well uncovered by experiments, our results demonstrate the advanced programmability of silicon quantum dot systems, delivering the practical guidelines for potential designs of quantum information processes based on electrically defined silicon quantum dot structures.
Implementing high-fidelity two-qubit gates in single-electron spin qubits in silicon double quantum dots is still a major challenge. In this work we employ analytical methods to design control pulses that generate high-fidelity entangling gates for quantum computers based on this platform. Using realistic parameters and initially assuming a noise-free environment, we present simple control pulses that generate cnot, cphase, and cz gates with average fidelities greater than 99.99% and gate times as short as 45 ns. Moreover, using the local invariants of the system's evolution operator, we show that a simple square pulse generates a cnot gate in less than 27 ns and with a fidelity greater than 99.99%. Last, we use the same analytical methods to generate two-qubit gates locally equivalent to CNOT\sqrt{\mathrm{CNOT}}CNOT​ and CZ\sqrt{\mathrm{CZ}}CZ​ that are used to implement simple two-piece pulse sequences that produce high-fidelity cnot and cz gates in the presence of low-frequency noise.
Implementing high-fidelity two-qubit gates in single-electron spin qubits in silicon double quantum dots is still a major challenge. In this work, we employ analytical methods to design control pulses that generate high-fidelity entangling gates for quantum computers based on this platform. Using realistic parameters, we present simple control pulses that generate CNOT, CPHASE, and CZ gates with average fidelities greater than 99.99% and gate times as short as 45 ns. Moreover, using the local invariants of the system's evolution operator, we show that a simple square pulse generates a CNOT gate in less than 27 ns and with a fidelity greater than 99.99%. Last, we use the same analytical methods to generate two-qubit gates locally equivalent to CNOT\sqrt{CNOT}CNOT​ and CZ\sqrt{CZ}CZ​ that are used to implement simple two-piece pulse sequences that produce high-fidelity CNOT and CZ gates in the presence of low-frequency noise.
Electron spins in Si are an attractive platform for quantum computation, backed with their scalability and fast, high-fidelity quantum logic gates. Despite the importance of two-dimensional integration with efficient connectivity between qubits for medium- to large-scale quantum computation, however, a practical device design that guarantees qubit addressability is yet to be seen. Here, we propose a practical 3 × 3 quantum dot device design and a larger-scale design as a longer-term target. The design goal is to realize qubit connectivity to the four nearest neighbors while ensuring addressability. We show that a 3 × 3 quantum dot array can execute four-qubit Grover's algorithm more efficiently than the one-dimensional counterpart. To scale up the two-dimensional array beyond 3 × 3, we propose a novel structure with ferromagnetic gate electrodes. Our results showcase the possibility of medium-sized quantum processors in Si with fast quantum logic gates and long coherence times.