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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A Parametric EDA Method for Coplanar Waveguide Channel Recognition and Air-Bridge Construction in Quantum Chip Design

Yanghepu Li, Shengming Ma, Jonathan Allcock, Tianyu Zhang, Xiong Xu, Sainan Huai, Shengyu Zhang

Published Apr 26, 2024• 1 citation
Publisher

Abstract

Coplanar Waveguides (CPW) are ideally suited for coherently interfacing resonators with superconducting qubits. However, integrating CPWs with circuit elements on quantum chips involves curvature and discontinuities of the central conductors and corresponding ground planes, which may generate undesired parasitic modes. Experiments have demonstrated that air-bridges can effectively suppress this unwanted effect. Nevertheless, as quantum processors increase in size, manual air-bridge placement on the chip layout becomes increasingly time-consuming and error-prone. Automation of this process is therefore highly desirable, especially when the center line (channel) of the CPWs is not pre-established. In this paper we propose a parametric EDA method for coplanar waveguide channel identification and air-bridge construction in quantum chips. Our approach applies to both separated and full-package air-bridges and scales efficiently, with running time linear in the number of points and quadratic in the number of arcs in the corresponding chip layout. We evaluate our approach on a set of open-source quantum chip layouts, generating air-bridges in times ranging from 0.05 to 0.5 seconds—a practical speedup of over 10,000 times compared to manual generation. Furthermore, We propose two original quantitative metrics, accuracy and overlap, and verify that our method yields reliable results, producing air-bridges in the required shapes and locations. We fabricate a 13-qubit chip using our method for air-bridge placement, and observe excellent performance with minimal microwave and flux crosstalk. This research enables rapid generation of air-bridges when CPW channels are not pre-specified, paving the way for more flexible, automated, and modular design of superconducting quantum EDA.

DOI
10.1109/tcad.2024.3394368

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Coplanar Waveguides (CPW) are ideally suited for coherently interfacing resonators with superconducting qubits. However, integrating CPWs with circuit elements on quantum chips involves curvature and discontinuities of the central conductors and corresponding ground planes, which may generate undesired parasitic modes. Experiments have demonstrated that air-bridges can effectively suppress this unwanted effect. Nevertheless, as quantum processors increase in size, manual air-bridge placement on the chip layout becomes increasingly time-consuming and error-prone. Automation of this process is therefore highly desirable, especially when the center line (channel) of the CPWs is not pre-established. In this paper we propose a parametric EDA method for coplanar waveguide channel identification and air-bridge construction in quantum chips. Our approach applies to both separated and full-package air-bridges and scales efficiently, with running time linear in the number of points and quadratic in the number of arcs in the corresponding chip layout. We evaluate our approach on a set of open-source quantum chip layouts, generating air-bridges in times ranging from 0.05 to 0.5 seconds—a practical speedup of over 10,000 times compared to manual generation. Furthermore, We propose two original quantitative metrics, accuracy and overlap, and verify that our method yields reliable results, producing air-bridges in the required shapes and locations. We fabricate a 13-qubit chip using our method for air-bridge placement, and observe excellent performance with minimal microwave and flux crosstalk. This research enables rapid generation of air-bridges when CPW channels are not pre-specified, paving the way for more flexible, automated, and modular design of superconducting quantum EDA.
Superconducting quantum electrical circuit based on Co-planar waveguide technology is considered one of the most promising candidates for practical realization of a\nquantum computer in future. For purpose of designing a multi-qubit quantum processor which is the heart of a quantum computer, it is required to couple qubits to a large number of superconducting transmission lines and resonators. Placing all these transmission lines and\nresonators in a practical design unavoidably creates bending and discontinuities in the ground\nplanes which have higher order parasitic modes that can be excited. These undesired parasitic\nmodes are detrimental for quantum measurement, for example during readout of a qubit.\nUnwanted modes can easily interfere with a resonator frequency when coupling to the qubit.\nThese parasitic modes can propagate throughout CPW structure and make unequal ground\npotential at the corresponding ground planes. The easiest way to suppress these parasitic\nmodes is to connect two unequal ground potential with superconducting air-bridges in order\nto bring them under equal potential in superconducting state. However, connecting airbridges on top of CPW adds shunt capacitor which may cause undesired reflection in the\nCPW.\nIn this thesis work, we designed superconducting air-bridges on top of\nsuperconducting CPW transmission line which is a subsystem of large quantum electrical\ncircuit. Our focus was to reduce added shunt capacitance by choosing the right height of these\nair-bridges. To keep the reflection coming from the air-bridge at minimum level, an airbridge\nheight of 8.5μm~15μm was chosen. The performance was verified by EM simulation\nand these heights were selected for device fabrication. We developed a new fabrication\nmethod for processing 8.5μm~15μm high aluminum air-bridges for quantum electrical\ncircuits. The method is compatible with the quantum circuit and easily reproducible. Finally,\ninput reflection measurement (S11) at cryogenic temperature was performed for 8.5μm high,\n300μm long aluminum air-bridges with aluminum CPW transmission line. Negligible amount\nof input reflection (S11) was observed from these measurements which is consistent with the\nresult of EM simulation.
Superconducting coplanar waveguide (CPW) can be widely used as two-dimensional (2D) resonator, transmission line or feedline, providing an important component for superconducting quantum circuit which is a promising candidate for quantum information processing. Due to the discontinuities and asymmetries in the ground planes, CPW usually exhibits the spurious resonance, which is a common source of decoherence in circuit quantum electrodynamics experiments. To mitigate the spurious resonance, we fabricated superconducting aluminum air-bridges on Nb CPW. The fabricated air-bridges are approximately 3 μm high and up to 120 μm long. Compared with other methods, the fabrication procedures of our air-bridges are simpler, and the air-bridge can withstand strong ultrasound.
Proper grounding between different ground planes in coplanar superconducting qubit circuits is important to avoid spurious resonances which increase decoherence. Here, the authors present a possible solution to suppress such undesired modes using superconducting aluminum air-bridges which have been fabricated on top of aluminum coplanar waveguide transmission lines. 3D electromagnetic simulations were done to guide the design of the air-bridges such that the input reflection (S11) of the bridges was kept at a minimum level. A fabrication method based on optical lithography techniques was developed and it resulted in air-bridges with a height of approximately 10 μm and lengths of up to 500 μm. The method can be generalized to arbitrary length air-bridge with heights even exceeding 15 μm.
Scaling up superconducting quantum processors necessitates the use of a high routing density for readout and control lines, relying on low-loss interconnects to maintain design flexibility and device performance. We propose and demonstrate a universal subtractive fabrication process for air bridges based on an aluminum hard mask and niobium as the superconducting film. Using this technology, we fabricate superconducting coplanar waveguide resonators incorporating several niobium air bridges in and across their center conductors. Through rigorous cleaning methods, we achieve mean internal quality factors in the single-photon limit exceeding Q int = 8.2 × 10 6 . Notably, the loss per air bridge remains below the detection threshold of the resonators. Due to the larger superconducting energy gap of niobium, compared with conventional aluminum air bridges, our approach enables stable performance at elevated temperatures and magnetic fields, which we experimentally confirm in temperatures up to 3.9 K and in a magnetic field of up to 1.60 T. Additionally, we utilize air bridges to realize low-loss vacuum-gap capacitors and demonstrate their successful integration in transmon qubits by achieving median qubit lifetimes of T 1 = 51.6 μ s .
Superconducting quantum computing systems, including coplanar waveguide (CPW) resonators and qubits, are highly susceptible to energy dissipation from two-level systems (TLS) within bulk and interfacial dielectrics. CPW resonators serve as an ideal platform for characterizing these material losses at the single-photon excitation level. Building on recent experimental evidence that interface engineering can mitigate TLS losses, this study employs simulations to evaluate resonator quality factors across various interface modifications. Our results demonstrate that reducing losses at the substrate–air (SA) interface can increase the internal quality factor Qi by up to three orders of magnitude. While etching the SA interface also enhances Qi, material loss remains the dominant dissipation mechanism. Furthermore, we find that other lossy interfaces have a significantly smaller impact on the quality factor compared to the SA interface. These simulation results align with established experimental findings, providing a robust framework for refining resonator design. This work offers precise guidelines for TLS mitigation, essential for enhancing coherence times and developing more reliable superconducting quantum processors.
Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.