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Optimizing Interface Dielectric Loss in Superconducting Coplanar Waveguide Resonators for Improved Quantum Circuit Coherence

Omar A. Saleh, Saleem G. Rao, Mohammed Alghadeer, Ahmed Abdelmottaleb Omar, Muhamad Felemban

Published Feb 18, 2026• 0 citations
Publisher

Abstract

Superconducting quantum computing systems, including coplanar waveguide (CPW) resonators and qubits, are highly susceptible to energy dissipation from two-level systems (TLS) within bulk and interfacial dielectrics. CPW resonators serve as an ideal platform for characterizing these material losses at the single-photon excitation level. Building on recent experimental evidence that interface engineering can mitigate TLS losses, this study employs simulations to evaluate resonator quality factors across various interface modifications. Our results demonstrate that reducing losses at the substrate–air (SA) interface can increase the internal quality factor Qi by up to three orders of magnitude. While etching the SA interface also enhances Qi, material loss remains the dominant dissipation mechanism. Furthermore, we find that other lossy interfaces have a significantly smaller impact on the quality factor compared to the SA interface. These simulation results align with established experimental findings, providing a robust framework for refining resonator design. This work offers precise guidelines for TLS mitigation, essential for enhancing coherence times and developing more reliable superconducting quantum processors.

DOI
10.3390/technologies14020128

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Superconducting quantum computing systems, including coplanar waveguide (CPW) resonators and qubits, are highly susceptible to energy dissipation from two-level systems (TLS) within bulk and interfacial dielectrics. CPW resonators serve as an ideal platform for characterizing these material losses at the single-photon excitation level. Building on recent experimental evidence that interface engineering can mitigate TLS losses, this study employs simulations to evaluate resonator quality factors across various interface modifications. Our results demonstrate that reducing losses at the substrate–air (SA) interface can increase the internal quality factor Qi by up to three orders of magnitude. While etching the SA interface also enhances Qi, material loss remains the dominant dissipation mechanism. Furthermore, we find that other lossy interfaces have a significantly smaller impact on the quality factor compared to the SA interface. These simulation results align with established experimental findings, providing a robust framework for refining resonator design. This work offers precise guidelines for TLS mitigation, essential for enhancing coherence times and developing more reliable superconducting quantum processors.
© 2019 American Physical Society. Superconducting quantum-computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLSs) in bulk and interfacial dielectrics. An understanding of these losses is critical to improving performance in superconducting circuits. In this work, we present a method for quantifying the TLS losses of different bulk and interfacial dielectrics present in superconducting coplanar-waveguide (CPW) resonators. By combining statistical characterization of sets of specifically designed CPW resonators on isotropically etched silicon substrates with detailed electromagnetic modeling, we determine the separate loss contributions from individual material interfaces and bulk dielectrics. This technique for analyzing interfacial TLS losses can be used to guide targeted improvements to qubits, resonators, and their superconducting fabrication processes.
In planar superconducting quantum circuits, two-level system (TLS) defects within amorphous dielectrics at various circuit interfaces, including substrate–metal (SM) and air-interfaces, are a critical source of decoherence. We employed molecular self-assembled monolayer (SAM) at different interfaces to mitigate TLS losses in superconducting coplanar waveguide (CPW) resonators. Previous work has reported an increase in the resonator quality factor when a SAM is applied to air-interfaces, but a contrasting decrease is observed when the SAM is applied to the metal–substrate interfaces. To investigate the reason behind this decrease, we fabricated and characterized niobium (Nb)-based CPW resonator chips on silicon substrates, both with and without a SAM at the SM interface. Quality factor measurements performed at 100 mK across a wide range of driving powers confirmed that the presence of the SAM at the SM interface led to a reduction in the quality factor. This observed decrease is attributed to an increased TLS defect density, as suggested by the topography of niobium deposited on the SAM. Our findings demonstrate that the roughness of the deposited Nb at the SM interface, which is influenced by the SAM, significantly impacts the density of TLS defects at this interface. Furthermore, simulations of TLS losses in CPW resonators supported our experimental observations by evaluating resonator quality factors under various interface modifications, particularly showing a decrease in the quality factor when the SM interface exhibited high loss.
Superconducting coplanar-waveguide (CPW) resonators are one of the key devices in circuit quantum electrodynamics (cQED). Their performance can be limited by dielectric losses in the substrate and in the material interfaces. Reliable modeling is required to aid in the design of low-loss CPW structures for cQED. We analyze the geometric dependence of the dielectric losses in CPW structures using finite-element modeling of the participation ratios of the lossy regions. In a practical scenario, uncertainties in the the dielectric constants and loss tangents of these regions introduce uncertainties in the theoretically predicted participation ratios. We present a method for combining loss simulations with measurements of two-level-system-limited quality factors and resonance frequencies of CPW resonators. Namely, we solve an inverse problem to find model parameters producing the measured values. High quality factors are obtainable by properly designing the cross-sectional geometries of the CPW structures, but more accurate modeling and design methods for low-loss CPW resonators are called for major future improvements. Our nonlinear optimization methodology for solving the aforementioned inverse problem is a step in this direction.
Superconducting coplanar waveguide (SCPW) resonators, key components for quantum computing and sensing applications, require a high internal quality factor ( Q i ) for effective qubit readout and quantum sensing applications. Minimizing two-level system (TLS) losses, particularly at material interfaces, is critical for gatemon and topological qubits operating at low temperatures and in high magnetic fields. NbTi, a superconducting alloy with a high upper critical field, enables SCPW resonators resilient to such conditions. We fabricated NbTi SCPW resonators on Si/SiO 2 substrates and systematically characterized their TLS-limited quality factors as functions of temperature and microwave photon number. Our results demonstrate that NbTi-based SCPWs on Si/SiO 2 substrates provide a promising platform for developing next-generation quantum circuits. • Successfully fabricated NbTi SCPW resonators on Si/SiO 2 substrates. • Characterized NbTi SCPW across temperature and photon ranges for quantum apps. • Achieved record TLS-limited quality factor Q TLS,0 = 9.21 × 10 4 for SCPW on Si/SiO 2 . • NbTi SCPW on Si/SiO 2 is promising for gatemon and topological qubits.
Improving the performance of superconducting qubits and resonators generally results from a combination of materials and fabrication process improvements and design modifications that reduce device sensitivity to residual losses. One instance of this approach is to use trenching into the device substrate in combination with superconductors and dielectrics with low intrinsic losses to improve quality factors and coherence times. Here, we demonstrate titanium nitride coplanar waveguide resonators with mean quality factors exceeding two million and controlled trenching reaching 2.2 μm in the silicon substrate. Additionally, we measure sets of resonators with a range of sizes and trench depths and compare these results with finite-element simulations to demonstrate quantitative agreement with a model of interface dielectric loss. We then apply this analysis to determine the extent to which trenching can improve resonator performance.
In planar superconducting circuits, decoherence due to materials imperfections, especially two-level-system (TLS) defects at different interfaces, is a primary hurdle for advancing quantum computing and sensing applications. Traditional methods for mitigating TLS loss, such as etching oxide layers at metal and substrate interfaces, have proven to be inadequate due to the persistent challenge of oxide regrowth. In this work, we introduce a novel approach that employs molecular self-assembled monolayers (SAMs) to chemically bind at different interfaces of superconducting circuits. This technique is specifically tested here on coplanar waveguide (CPW) resonators, in which this method not only impedes oxide regrowth after surface etching but can also tailors the dielectric properties at different resonators interfaces. The deployment of SAMs results in a consistent improvement in the measured quality factors across multiple resonators, surpassing those with only oxide-etched resonators. The efficiency of our approach i3s supported by microwave measurements of multiple devices conducted at millikelvin temperatures and correlated with detailed X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) characterizations of SAM-passivated resonators. The compatibility of SAMs materials with the established fabrication techniques offers a promising route to improve the performance of superconducting quantum devices.