Single-qubit randomized benchmarking of flux-tuneable transmons: a test time analysis
Thorsten Last, Yevheniia Cheipesh, Konstantin Lehman, Vraj Patel, Sebastian Hähnle, Timo R. van Abswoude, Adam Lawrence, Anna Shchygol, Kelvin Loh, Garrelt Alberts, Michiel Adriaan Rol
The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.
The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.
This thesis mainly summarizes two experiments that relate to building a quantum computer out of superconducting transmon qubits. Transmon qubits have emerged as one of the foremost solid state qubits, realizing processors with more than ten qubits and demonstrating small scale quantum algorithms as well as quantum error correction schemes. Right now, there is a race between different academic and industry research groups to scale up transmon qubit processors. The first experiment was a demonstration of qubit control by selective broadcasting in order to reduce the scaling of expensive electronics with the number of qubits for individual single-qubit control. We demonstrated that we can bring two transmon qubits to the same frequency (combining fabrication accuracy and in-situ fine tuning) and use the same hardware to control both, routing the pulses with a nanosecond-timescale vector switch matrix. Despite the compromises required by this technique, we show a scalable path to single qubit control beyond the threshold required for quantum error correction. In benchmarking, we take into account gate leakage due to the fact that transmons are fundamentally multi-level systems. In the second experiment we establish entanglement between two transmon qubits on different chips. We use an entanglement by measurement scheme and demonstrate that we can overcome minor fabrication imperfections by shaping our measurement pulses. Ultimately, performance is mainly limited by photon loss between the chips and up to the amplification chain. This entanglement mediated by traveling photons could be used to make a distributed transmon processor where computations are spread across several chip modules. This modularity could enable connectivities that cannot be realized on chip and ease fabrication requirements, as modules could be individually fabricated and selected. Thus, both of these experiments fit into the larger effort to converge on the hardware, control equipment and architecture of a future large-scale transmon quantum computer. Other experiments I contributed to are summarized in the conclusion chapter to show the diverse physics that can be studied in cQED experiments.
Ternary quantum processors offer significant potential computational advantages over conventional qubit technologies, leveraging the encoding and processing of quantum information in qutrits (three-level systems). To evaluate and compare the performance of such emerging quantum hardware it is essential to have robust benchmarking methods suitable for a higher-dimensional Hilbert space. We demonstrate extensions of industry standard randomized benchmarking (RB) protocols, developed and used extensively for qubits, suitable for ternary quantum logic. Using a superconducting five-qutrit processor, we find an average single-qutrit process infidelity of 3.8×10^{-3}. Through interleaved RB, we characterize a few relevant gates, and employ simultaneous RB to fully characterize crosstalk errors. Finally, we apply cycle benchmarking to a two-qutrit CSUM gate and obtain a two-qutrit process fidelity of 0.85. Our results present and demonstrate RB-based tools to characterize the performance of a qutrit processor, and a general approach to diagnose control errors in future qudit hardware.
Recent experiments have demonstrated superconducting transmon qubits with semiconductor nanowire Josephson junctions. These hybrid gatemon qubits utilize field effect tunability characteristic of semiconductors to allow complete qubit control using gate voltages, potentially a technological advantage over conventional flux-controlled transmons. Here, we present experiments with a two-qubit gatemon circuit. We characterize qubit coherence and stability and use randomized benchmarking to demonstrate single-qubit gate errors below 0.7% for all gates, including voltage-controlled Z rotations. We show coherent capacitive coupling between two gatemons and coherent swap operations. Finally, we perform a two-qubit controlled-phase gate with an estimated fidelity of 91%, demonstrating the potential of gatemon qubits for building scalable quantum processors.
As quantum processors grow, new performance benchmarks are required to capture the full quality of the devices at scale. While quantum volume is an excellent benchmark, it focuses on the highest quality subset of the device and so is unable to indicate the average performance over a large number of connected qubits. Furthermore, it is a discrete pass/fail and so is not reflective of continuous improvements in hardware nor does it provide quantitative direction to large-scale algorithms. For example, there may be value in error mitigated Hamiltonian simulation at scale with devices unable to pass strict quantum volume tests. Here we discuss a scalable benchmark which measures the fidelity of a connecting set of two-qubit gates over N qubits by measuring gate errors using simultaneous direct randomized benchmarking in disjoint layers. Our layer fidelity can be easily related to algorithmic run time, via γ defined in Ref.\cite{berg2022probabilistic} that can be used to estimate the number of circuits required for error mitigation. The protocol is efficient and obtains all the pair rates in the layered structure. Compared to regular (isolated) RB this approach is sensitive to crosstalk. As an example we measure a N=80(100) qubit layer fidelity on a 127 qubit fixed-coupling "Eagle" processor (ibm\_sherbrooke) of 0.26(0.19) and on the 133 qubit tunable-coupling "Heron" processor (ibm\_montecarlo) of 0.61(0.26). This can easily be expressed as a layer size independent quantity, error per layered gate (EPLG), which is here 1.7×10−2(1.7×10−2) for ibm\_sherbrooke and 6.2×10−3(1.2×10−2) for ibm\_montecarlo.
Quantum information processing holds the promise of a paradigm shift in computational power for specific problem classes. While contemporary quantum processors operate in the Noisy Intermediate-Scale Quantum (NISQ) regime and remain highly susceptible to errors, ongoing experimental efforts on these near-term devices are crucial for advancing the underlying technology. Among the various hardware implementations, superconducting quantum circuits stand out as one of the most robust architectures for scalable quantum technologies. Nevertheless, the primary bottleneck in these systems is the fragility of quantum information: interactions with the environment inevitably perturb the quantum states, a phenomenon known as decoherence. This rapid loss of stored information imposes a fundamental limit on the time available to reliably execute computations on these devices. Within this context, this thesis focuses on the comprehensive experimental characterization of a planar chip featuring isolated, fixed-frequency superconducting transmon qubits. The measurements were conducted in a cryogenic environment, relying on a dilution refrigerator to maintain the device at millikelvin temperatures. To probe the quantum system under these conditions, custom measurement scripts were developed to operate state-of-the-art microwave control electronics (Keysight Quantum Control System), establishing full control over pulse generation, signal acquisition, and digital demodulation. The experimental workflow systematically mapped the physical properties of the device through a progressive series of characterization steps. Initial spectroscopic techniques probed the coupled resonator-qubit system, identifying its fundamental transition frequencies and relevant energy scales. Building upon these frequency-domain measurements, coherent control was achieved by calibrating resonant microwave pulses to drive single-qubit rotations, enabling the reliable preparation of the qubit in excited or coherent superposition states. Finally, specific time-domain protocols were implemented to evaluate the operational limits of the device. By executing standard pulse sequences, the characteristic decoherence metrics of the system, namely the longitudinal energy relaxation time (T1) and the inhomogeneous dephasing time (T2*), were successfully extracted, providing a quantitative assessment of the qubit's overall performance and establishing a baseline for future implementations of more advanced quantum control protocols.
Superconducting qubit parameters drift on sub-second timescales, motivating calibration and benchmarking techniques that can be executed on millisecond timescales. We demonstrate an on-FPGA workflow that co-locates pulse generation, data acquisition, analysis, and feed-forward, eliminating CPU round trips. Within this workflow, we introduce sparse-sampling and on-FPGA inference tools, including computationally efficient methods for estimation of exponential and sine-like response functions, as well as on-FPGA implementations of Nelder-Mead optimization and golden-section search. These methods enable low-latency primitives for readout calibration, spectroscopy, pulse-amplitude calibration, coherence estimation, and benchmarking. We deploy this toolset to estimate T1 in 10 ms, optimize readout parameters in 100 ms, optimize pulse amplitudes in 1 ms, and perform Clifford randomized gate benchmarking in 107 ms on a flux-tunable superconducting transmon qubit. Running a closed-loop on-FPGA recalibration protocol continuously for 6 hours enables more than 74,000 consecutive recalibrations and yields gate errors that consistently retain better performance than the baseline initial calibration. Correlation analysis shows that recalibration suppresses coupling of gate error to control-parameter drift while preserving a coherence-linked performance. Finally, we quantify uncertainty versus time-to-decision under our sparse sampling approaches and identify optimal parameter regimes for efficient estimation of qubit and pulse parameters.