Abstract Reversible logic synthesis is becoming a significant research component for post-CMOS computing devices, particularly quantum computing. In this work we connect the reversible logic synthesis problem to sorting algorithms. Reversible logic has emerged as a promising technology in recent years, with applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical gates AND, OR, and XOR are not reversible. This paper employs the control swap gate to implement a 2x2 switch. In multiprocessor system different computing operations are performed concurrently to get higher throughput. Sorting network can be used to tie up different parts of a large complex system efficiently with least amount of hardware to perform concurrent operations. A sorting network can be built using a multiple input and multiple output switching network. Following the implementation of the 2x2 switch, a bitonic sorting circuit is designed. The goal of developing a reversible sorting circuit is to reduce power consumption while maintaining reliable communication. The bitonic sorting circuit was successfully implemented, and the output was simulated in IBM qiskit. This presents efficient sorting circuit that can sort binary numbers in ascending/descending order.
Abstract Reversible logic synthesis is becoming a significant research component for post-CMOS computing devices, particularly quantum computing. In this work we connect the reversible logic synthesis problem to sorting algorithms. Reversible logic has emerged as a promising technology in recent years, with applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical gates AND, OR, and XOR are not reversible. This paper employs the control swap gate to implement a 2x2 switch. In multiprocessor system different computing operations are performed concurrently to get higher throughput. Sorting network can be used to tie up different parts of a large complex system efficiently with least amount of hardware to perform concurrent operations. A sorting network can be built using a multiple input and multiple output switching network. Following the implementation of the 2x2 switch, a bitonic sorting circuit is designed. The goal of developing a reversible sorting circuit is to reduce power consumption while maintaining reliable communication. The bitonic sorting circuit was successfully implemented, and the output was simulated in IBM qiskit. This presents efficient sorting circuit that can sort binary numbers in ascending/descending order.
Background: The synthesis of reversible logic has gained prominence as a crucial research area, particularly in the context of post-CMOS computing devices, notably quantum computing. Objective: To implement the bitonic sorting circuit, 2x2 switch, is used. The overarching objective of implementing a reversible sorting circuit is to mitigate power consumption while promising secure communication. The successful implementation of the bitonic sorting circuit utilizing the proposed 2x2 switch is validated through simulations conducted in IBM Qiskit. Methods: This study begins by employing the control swap gate to implement a 2x2 switch, aimed at enabling concurrent computing operations within multiprocessor systems to enhance throughput. Subsequently, following the successful implementation of the 2x2 switch, the study proceeds to design a bitonic sorting circuit. Results: Bitonic sort using a 2x2 switch on the IBM Quantum Experience (IBMQ) platform via the QISKit SDK in Python 3.6. Specifically, Qiskit v0.29.0 is utilized, with OpenQASM. OpenQASM serves as the quantum assembly and instruction language. Conclusion: This work presents a methodology for constructing a 2x2 switch, utilizing a reversible control swap gate as its core component. Additionally, it demonstrates the intricate development and implementation of a bitonic sorting circuit, capitalizing on this innovative switch architecture.
Abstract — Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in designing of more complex system having reversible circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents the data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
The emergence of quantum computers in the last decade has generated research interest in applications such as quantum sorting. Quantum sorting plays a critical role in creating ordered sets of data that can be better utilized, e.g., quantum ordered search or quantum network switching. In this paper, we propose a quantum sorting algorithm that combines highly parallelizable bitonic merge networks with perfect shuffle permutations (PSP), for sorting data represented in the quantum domain. The combination of bitonic networks with PSP improves the temporal complexity of bitonic merge sorting which is critical for reducing decoherence effects for quantum processing. We present space-efficient quantum circuits that can be used for quantum bit comparison and permutation. We also present a reconfigurable hardware quantum emulator for prototyping the proposed quantum algorithm. The emulator has a fully-pipelined architecture and supports double-precision floating-point computations, resulting in high throughput and accuracy. The proposed hardware architectures are implemented on a high-performance reconfigurable computer (HPRC). In our experiments, we emulated quantum sorting circuits of up to 31 fully-entangled quantum bits on a single FPGA node of the HPRC platform. To the best of our knowledge, our effort is the first to investigate a reconfigurable hardware emulation of quantum sorting using bitonic networks and perfect shuffle.
Quantum computing is at the leading edge of advanced technology that uses quantum phenomena such as entanglement and super position to solve complex problems. One of the main application is to built comparator circuit to do arithmetic operations at stipulated time. Based on this our research is to propose the design and implementation of one-bit and two-bit quantum comparators using IBM Qiskit, which is formly compared with classical comparator. Also this work represents a comprehensive overview of the techniques required to optimize and design quantum comparator circuits using real quantum simulators. The results obtained from simulation promises the comparison accuracy with classical results. From the circuit designed it is inferred that the hardware complexity is very much reduced compared to classical comparator, which are tabulated in terms of number of quantum gates. The proposed method can further be extended to generate higher order comparator circuits. These results may form the basis for further research and development that will support the advancement of quantum computing and algorithms.