In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1
In recent years, research in reversible logic has attracted significance attention leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose Design of Efficient Reversible Binary Comparator. The input circuit and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator are designed using input circuit as first stage and one-bit comparator cell as second stage and so on. The Power consumption, Delay, Garbage outputs and Constant inputs are computed. It is observed that the Quantum cost and Garbage output values are less in the proposed technique compared to the existing approaches.
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,
Abstract — Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper provides the basic reversible logic gates, which in designing of more complex system having reversible circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents the data relating to the primitive reversible gates which are available in literature and helps researches in designing higher complex computing circuits using reversible gates.
Reversible logic is gaining increasing significance in diverse research areas, including quantum computing, nanotechnology, and optical computing. The exploration of reversible gates has emerged as a cutting-edge research area, driving a wave of innovative developments aimed at maximizing resource efficiency. This work focused on creating highly efficient 2-bit, 8-bit, and 64-bit comparators, leveraging the advantages of reversible logic gates. The results obtained from the comparative analysis demonstrate substantial improvements in energy efficiency and computational speed compared to other architectures. The proposed design demonstrated superior performance with reduced quantum cost and delay while minimizing garbage outputs. Specifically, the quantum costs of the 2-bit, 8-bit, and 64-bit comparators were measured to be 20, 128, and 1136, respectively. These outcomes suggest substantial enhancements in a variety of parameters, which ultimately will result in a more efficient and effective design. The functionality of the designed comparator tree was validated using Xilinx Vivado 2022.2 and implemented in Verilog HDL.