Abstract Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes to ensure fault-tolerance in quantum circuits. However, it is important to note that T-gates come at a considerable computational cost. Our methodology revolves around a comprehensive study of these comparator circuits from a bottom-up perspective. We delve deep into the intricate details of these circuits, dissecting their underlying components and functions. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We have expressed the proposed circuits in Clifford+T gates to render them fault-tolerant while concurrently minimising the utilisation of T-gates, thereby mitigating the associated computational costs. By strategically reducing the number of T-gates used and improving their efficiency, we not only mitigate computational overhead, but also ensure the robustness of these circuits in the face of errors and environmental disturbances.Abstract Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes to ensure fault-tolerance in quantum circuits. However, it is important to note that T-gates come at a considerable computational cost. Our methodology revolves around a comprehensive study of these comparator circuits from a bottom-up perspective. We delve deep into the intricate details of these circuits, dissecting their underlying components and functions. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We have expressed the proposed circuits in Clifford+T gates to render them fault-tolerant while concurrently minimising the utilisation of T-gates, thereby mitigating the associated computational costs. By strategically reducing the number of T-gates used and improving their efficiency, we not only mitigate computational overhead, but also ensure the robustness of these circuits in the face of errors and environmental disturbances.

Oct 10, 20233 citations

Efficient design of a quantum absolute-value circuit using Clifford+T gates

Francisco José Orts, Gloria Ortega, Elías F. Combarro +3 more

Abstract Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two’s complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation.Abstract Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two’s complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation.

The Journal of SupercomputingMar 18, 20236 citations

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation

Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay +3 more

The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.

IEEE International Symposium on Multiple-Valued Logic (ISMVL)May 1, 201618 citations

Fault-tolerant quantum algorithm for dual-threshold image segmentation

Luis O. López, Francisco José Orts, Gloria Ortega +2 more

Abstract The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm is based on Clifford+T gates. Because T gates add fault tolerance but have the trade-off of having a much higher cost than other quantum gates,our focus has been on reducing the number of T gates. This has allowed adding noise tolerance, computational cost reduction and fault toleranceto the state-of-the-art dual-threshold segmentation circuits. Sincethe dual-threshold image segmentation involves the comparison operation,as part of this work we have implemented two comparator circuits.These circuits optimise the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature.Abstract The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm is based on Clifford+T gates. Because T gates add fault tolerance but have the trade-off of having a much higher cost than other quantum gates,our focus has been on reducing the number of T gates. This has allowed adding noise tolerance, computational cost reduction and fault toleranceto the state-of-the-art dual-threshold segmentation circuits. Sincethe dual-threshold image segmentation involves the comparison operation,as part of this work we have implemented two comparator circuits.These circuits optimise the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature.

The Journal of SupercomputingMar 15, 202310 citations

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder

Himanshu Thapliyal, Edgard Muñoz‐Coreas, Vladislav Khalus

Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of $54.34 \%$ and $37.21 \%$ , respectively. The proposed QCLAs for in-place addition achieve average T gate savings of $72.11 \%$ and $35.87 \%$ Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of $54.34 \%$ and $37.21 \%$, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of $72.11 \%$ and $35.87 \%$

arXiv:2004.01826Apr 4, 20206 citations

Designing quantum adder circuits and evaluating their error performance

Amlan Chakrabarti, Susmita Sur‐Kolay

With the advent of efficient quantum algorithms and technological advances, design of quantum circuits has gained importance. Minimization of the gate count and the number of gate levels are the two major objectives in quantum circuit design. The peculiar nature of quantum decoherence that leads to quantum errors mandates completion of all the quantum gate operations within a time bound, hence reduction in the gate count and the number of circuit levels leads to lowering the errors and the overall cost in quantum circuits. In this paper, we propose the design of adder circuits using CNOT and CkNOT gates, with significant reduction in gate count and number of gate levels over their existing counterparts in the literature. We then present a software model for evaluating errors in quantum computing circuits and employ it for evaluating the error performance of our proposed quantum adder circuits.With the advent of efficient quantum algorithms and technological advances, design of quantum circuits has gained importance. Minimization of the gate count and the number of gate levels are the two major objectives in quantum circuit design. The peculiar nature of quantum decoherence that leads to quantum errors mandates completion of all the quantum gate operations within a time bound, hence reduction in the gate count and the number of circuit levels leads to lowering the errors and the overall cost in quantum circuits. In this paper, we propose the design of adder circuits using CNOT and CkNOT gates, with significant reduction in gate count and number of gate levels over their existing counterparts in the literature. We then present a software model for evaluating errors in quantum computing circuits and employ it for evaluating the error performance of our proposed quantum adder circuits.

International Conference on Electronic DesignDec 1, 20089 citations

54.34 \%

and

37.21 \%

, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of

72.11 \%

and

35.87 \%