The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.
The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.
The Clifford+T gate library consisting of Hadamard, T, and CNOT gates has attracted much interest in quantum circuit synthesis, particularly due to its applicability to fault tolerant realizations. Since fault tolerant implementations of the T gate have very high latency, recent work in this area is aiming at minimizing the number of T stages, referred to as the T-depth. In this paper, we present an approach to exploit additional ancilla qubits in the mapping of reversible circuits consistina of multiple controlled Toffoli gates (MCT gates) into califford+T quantum circuits, with the primary optimization objective to minimize the T-depth. Our proposed approach takes advantage of and generalizes earlier work on corresponding mapping algorithms. An experimental evaluation shows that our approach leads to a significant T-depth reduction compared to earlier approaches.
Abstract Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes to ensure fault-tolerance in quantum circuits. However, it is important to note that T-gates come at a considerable computational cost. Our methodology revolves around a comprehensive study of these comparator circuits from a bottom-up perspective. We delve deep into the intricate details of these circuits, dissecting their underlying components and functions. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We have expressed the proposed circuits in Clifford+T gates to render them fault-tolerant while concurrently minimising the utilisation of T-gates, thereby mitigating the associated computational costs. By strategically reducing the number of T-gates used and improving their efficiency, we not only mitigate computational overhead, but also ensure the robustness of these circuits in the face of errors and environmental disturbances.
The well-known 3-bit Hermitian gate (a Toffoli gate) has been implemented using Clifford + T circuits. Compared with the Peres gate, its implementation circuit requires more controlled-NOT (CNOT) gates. However, the Peres gate is not Hermitian. This paper reports four 3-bit Hermitian gates named LI gates. Whose realized circuits have the same T-count, T-depth, and CNOT-count as the Peres gate. Furthermore, two decomposition methods of a multiple control Toffoli (MCT) gate are proposed for different primary optimization goals. Then, we design the equality, less-than, and full comparators with the minimum circuit width using proposed Hermitian gates and optimized MCT gates. A fault-tolerant circuit is required for robust quantum computing. Clifford+T circuits are accepted solutions for fault-tolerant implementation. Considering T-count, T-depth, CNOT-count, and circuit width as the primary optimization goals, we design the optimized Clifford + T circuits of three comparators using LI gates and optimized MCT gates. Comparison and analysis show that the proposed comparators have better overall performances for T-count, T-depth, CNOT-count, and circuit width than the best-known comparators without quantum measurements.
In the last few years, tremendous improvement in the field of quantum computing has been witnessed. Although quantum technologies such as ion-trap, NMR, quantum dots have emerged as the promising platforms for implementing quantum circuits but these technologies have faced several design issues. One such important design problem is the nearest neighbor condition, which requires the qubits to interact with adjacent neighbors. This problem can be addressed by adding SWAP gates in the circuit. By doing so, the overhead in the circuit increases thus NN designs with minimum number of SWAP gates need to be developed. Focusing on this, here, in this work, we introduce a heuristic design method for efficient NN realization of quantum circuits in 2D architecture. Our NN transformation process is carried out in two phases, where initially in the first phase, the input circuit is mapped to 2D configuration using a qubit placement strategy and then in the second phase NN designs are obtained through SWAP gate insertion. At the end, the design algorithm has been evaluated over a large set of benchmark functions and the results are compared with some of the existing works. From this comparison, it is seen that our proposed method performs better than the reported works.
In the last few years, quantum computing has gained the attention of the researchers due to its ability to perform parallel and exponentially faster computation over classical computing. One of the prominent challenges for quantum circuits is to satisfy the nearest neighbor (NN) condition, i.e., the qubits of the computing gate must be placed adjacent. Based on this fact, here, in this paper, we have proposed a heuristic synthesis workflow to realize NN circuits in 2D grid configuration. The implemented approach has been evaluated over a broad range of benchmark circuits and we have reported the best results. To validate the efficiency of the stated approach, we have compared it with the previously reported works, an average improvement of 15.94%, 8.89% and 10.98% are obtained over the existing 2D works, and 44.72% and 70.35% are obtained over existing 1D works, respectively.
Reversible logic is essential in quantum computing due to its ability to preserve information and establish a one-to-one mapping between inputs and outputs. The Clifford+T gate set, known for supporting fault-tolerant quantum circuits, offers resilience against decoherence but introduces high implementation costs, particularly due to the T gate's resource intensity. In this work, we propose a new and efficient quantum multiplexer design, the Quantum Clifford T-MUX, designed entirely within the Clifford+T framework. This multiplexer minimizes T-count and avoids the use of ancillary qubits, both critical factors for practical, fault-tolerant quantum computing. As part of this architecture, we present a newly designed fault-tolerant Peres gate using only Clifford+T gates, which serves as a fundamental building block in the T-MUX construction. The proposed T-MUX achieves reduced T-count, no garbage output, and improved efficiency compared to traditional designs. These improvements position it as a valuable component for building scalable quantum Arithmetic Logic Units (ALUs), data buses, and memory systems. Overall, this work contributes toward the development of low-overhead, modular quantum control structures suited for near-term and long-term quantum computing architectures. The proposed circuit is simulated using the Quirk online tool, and the result confirms the accuracy of the design. This design achieves an average 35% improvement in T-Count without any constant input, compared to its counterpart, respectively.