With the advent of efficient quantum algorithms and technological advances, design of quantum circuits has gained importance. Minimization of the gate count and the number of gate levels are the two major objectives in quantum circuit design. The peculiar nature of quantum decoherence that leads to quantum errors mandates completion of all the quantum gate operations within a time bound, hence reduction in the gate count and the number of circuit levels leads to lowering the errors and the overall cost in quantum circuits. In this paper, we propose the design of adder circuits using CNOT and CkNOT gates, with significant reduction in gate count and number of gate levels over their existing counterparts in the literature. We then present a software model for evaluating errors in quantum computing circuits and employ it for evaluating the error performance of our proposed quantum adder circuits.
With the advent of efficient quantum algorithms and technological advances, design of quantum circuits has gained importance. Minimization of the gate count and the number of gate levels are the two major objectives in quantum circuit design. The peculiar nature of quantum decoherence that leads to quantum errors mandates completion of all the quantum gate operations within a time bound, hence reduction in the gate count and the number of circuit levels leads to lowering the errors and the overall cost in quantum circuits. In this paper, we propose the design of adder circuits using CNOT and CkNOT gates, with significant reduction in gate count and number of gate levels over their existing counterparts in the literature. We then present a software model for evaluating errors in quantum computing circuits and employ it for evaluating the error performance of our proposed quantum adder circuits.
Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of 54.34% and 37.21%, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of 72.11% and 35.87%
One of the critical limitations quantum computers are yet to overcome is quantum errors. Efforts have been made in quantum error correction fields to overcome them. However, since we are bound by the technology of this noisy intermediate-scale quantum era, it is important that we focus on the efficiency and optimization of our error correction circuits. In this paper, we present a way of extending quantum error correction circuits using quantum adders by utilizing the notion of majority voting over all the qubits. We use adder circuits and a comparator to achieve majority voting. We demonstrate how our proposed methodology exhibits a linear trend in the required number of quantum gates. Further, we confirm the accuracy and efficacy of our proposed methodology for optimizing the number of quantum gates through extensive simulation in IBM's Qiskit and compare them with existing literature.
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
Decoherence of quantum states is a major hurdle towards scalable and reliable quantum computing. Lower decoherence (i.e., higher fidelity) can alleviate the error correction overhead and obviate the need for energy-intensive noise reduction techniques e.g., cryogenic cooling. In this paper, we performed a noise-induced decoherence analysis of single and multi-qubit quantum gates using physics-based simulations. The analysis indicates that (i) decoherence depends on the input state and the gate type. Larger number of ∣1⟩ states worsen the decoherence; (ii) amplitude damping is more detrimental than phase damping; (iii) shorter depth implementation of a quantum function can achieve lower decoherence. Simulations indicate 20\% improvement in the fidelity of a quantum adder when realized using lower depth topology. The insights developed in this paper can be exploited by the circuit designer to choose the right gates and logic implementation to optimize the system-level fidelity.
Quantum computers are able to efficiently solve certain problems that are very computationally demanding or even intractable on classical computers. With recent advances in quantum computing hardware, we are entering an exciting era where it is becoming possible to execute ‘useful’ quantum algorithms. However, quantum computers will continue to be noisy for the foreseeable future. In this paper, quantum adder circuits are used to evaluate three simple error mitigation methods: (1) error correction through the use of replicated circuits and a voter circuit, (2) error detection by encoding, which involves expanding the qubit space and partitioning it into orthogonal subspaces consisting of correct and incorrect code words, and (3) error mitigation by reducing circuit depth at the expense of increasing the number of qubits. These three mitigation methods are what we dub replication, encoding, and simplification, respectively. We find simplification to be most effective for implementing the simple quantum adders on the IBM Quantum Experience, while replication increases the gate count and the error count on current quantum devices. The encoding methods used in this study proved to be not effective for even the simple adder circuits that were implemented, suggesting the need to study and evaluate more sophisticated error correcting schemes.